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74ACT573MTR View Datasheet(PDF) - STMicroelectronics

Part Name74ACT573MTR ST-Microelectronics
STMicroelectronics ST-Microelectronics
DescriptionOCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS (NON INVERTED)


74ACT573MTR Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
74ACT573
CAPACITIVE CHARACTERISTICS
Test Condition
Value
Symbol
Parameter
VCC
(V)
TA = 25°C
-40 to 85°C -55 to 125°C Unit
Min. Typ. Max. Min. Max. Min. Max.
CIN Input Capacitance 5.0
4
pF
COUT
Output
Capacitance
5.0
8
pF
CPD Power Dissipation
Capacitance (note 5.0
fIN = 10MHz
25
pF
1)
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit)
TEST CIRCUIT
TEST
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
CL = 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500or equivalent
RT = ZOUT of pulse generator (typically 50)
SWITCH
Open
2VCC
Open
5/11
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DESCRIPTION
The 74ACT573 is an advanced high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.
These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). While the LE inputs is held at a high level, the Q outputs will follow the data input .

■ HIGH SPEED: tPD = 5ns (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION:
   ICC = 4µA(MAX.) at TA=25°C
■ COMPATIBLE WITH TTL OUTPUTS
   VIH = 2V (MIN.), VIL = 0.8V (MAX.)
■ 50Ω TRANSMISSION LINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 24mA (MIN)
■ BALANCED PROPAGATION DELAYS:
   tPLH = tPHL
■ OPERATING VOLTAGE RANGE:
   VCC (OPR) = 4.5V to 5.5V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573
■ IMPROVED LATCH-UP IMMUNITY

 

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