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74ACT573MTR View Datasheet(PDF) - STMicroelectronics

Part Name74ACT573MTR ST-Microelectronics
STMicroelectronics ST-Microelectronics
DescriptionOCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS (NON INVERTED)


74ACT573MTR Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
74ACT573
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUTS (NON INVERTED)
s HIGH SPEED: tPD = 5ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4µA(MAX.) at TA=25°C
s COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN.), VIL = 0.8V (MAX.)
s 50TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74ACT573 is an advanced high-speed CMOS
OCTAL D-TYPE LATCH with 3 STATE OUTPUT
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C2MOS
technology.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
outputs will follow the data input .
PIN CONNECTION AND IEC LOGIC SYMBOLS
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
74ACT573B
74ACT573M
T&R
74ACT573MTR
74ACT573TTR
When the LE is taken low, the Q outputs will be
latched precisely or inversely at the logic level of D
input data. While the (OE) input is low, the 8
outputs will be in a normal logic state (high or low
logic level) and while high level the outputs will be
in a high impedance state.
This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
April 2001
1/11
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DESCRIPTION
The 74ACT573 is an advanced high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.
These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). While the LE inputs is held at a high level, the Q outputs will follow the data input .

■ HIGH SPEED: tPD = 5ns (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION:
   ICC = 4µA(MAX.) at TA=25°C
■ COMPATIBLE WITH TTL OUTPUTS
   VIH = 2V (MIN.), VIL = 0.8V (MAX.)
■ 50Ω TRANSMISSION LINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 24mA (MIN)
■ BALANCED PROPAGATION DELAYS:
   tPLH = tPHL
■ OPERATING VOLTAGE RANGE:
   VCC (OPR) = 4.5V to 5.5V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573
■ IMPROVED LATCH-UP IMMUNITY

 

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