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74ACT74 View Datasheet(PDF) - ON Semiconductor

Part Name74ACT74 ON-Semiconductor
ON Semiconductor ON-Semiconductor
DescriptionDual D−Type Positive Edge−Triggered Flip−Flop


74ACT74 Datasheet PDF : 12 Pages
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MC74AC74, MC74ACT74
DC CHARACTERISTICS
Symbol
Parameter
VIH
Minimum High Level
Input Voltage
VIL
Maximum Low Level
Input Voltage
VOH
Minimum High Level
Output Voltage
74ACT
74ACT
VCC
(V)
TA = +25°C
TA =
40°C to
+85°C
Typ Guaranteed Limits
4.5
1.5 2.0
2.0
5.5
1.5 2.0
2.0
4.5
1.5 0.8
0.8
5.5
1.5 0.8
0.8
4.5 4.49 4.4
4.4
5.5 5.49 5.4
5.4
VOL
Maximum Low Level
Output Voltage
4.5
3.86
3.76
5.5
4.86
4.76
4.5 0.001 0.1
0.1
5.5 0.001 0.1
0.1
4.5
0.36
0.44
5.5
0.36
0.44
IIN
Maximum Input
Leakage Current
5.5
±0.1
±1.0
DICCT
Additional Max. ICC/Input
5.5
0.6
1.5
IOLD
IOHD
†Minimum Dynamic
Output Current
5.5
75
5.5
75
ICC
Maximum Quiescent
Supply Current
5.5
4.0
40
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
Unit
Conditions
V
VOUT = 0.1 V
or VCC 0.1 V
V
VOUT = 0.1 V
or VCC 0.1 V
V
IOUT = 50 mA
*VIN = VIL or VIH
V
24 mA
IOH
24 mA
V
IOUT = 50 mA
*VIN = VIL or VIH
V
IOL
24 mA
24 mA
mA
VI = VCC, GND
mA
VI = VCC 2.1 V
mA
VOLD = 1.65 V Max
mA
VOHD = 3.85 V Min
mA
VIN = VCC or GND
AC CHARACTERISTICS (For Figures and Waveforms See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74ACT
74ACT
Symbol
Parameter
VCC*
(V)
TA = +25°C
CL = 50 pF
TA = 40°C
to +85°C
CL = 50 pF
Unit
Fig.
No.
Min Typ Max Min Max
fmax
Maximum Clock
Frequency
tPLH
Propagation Delay
CDn or SDn to Qn or Qn
tPHL
Propagation Delay
CDn or SDn to Qn or Qn
tPLH
Propagation Delay
CPn to Qn or Qn
tPHL
Propagation Delay
CPn to Qn or Qn
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
5.0 145 210
125
MHz
33
5.0 3.0 5.5 9.5 2.5 10.5 ns
36
5.0 3.0 6.0 10.0 3.0 11.5 ns
36
5.0 4.0 7.5 11.0 4.0 13.0 ns
36
5.0 3.5 6.0 10.0 3.0 11.5 ns
36
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Dual D−Type Positive Edge−Triggered Flip−Flop

  The MC74AC74/74ACT74 is a dual D−type flip−flop with Asynchronous Clear and Set inputs and complementary (Q,Q) outputs. Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input.
Asynchronous Inputs:
LOW input to SD(Set) sets Q to HIGH level
LOW input to CD(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CDand SDmakes both Q and QHIGH

Features
•Outputs Source/Sink 24 mA
•′ACT74 Has TTL Compatible Inputs
•Pb−Free Packages are Available

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