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74ACT74 View Datasheet(PDF) - ON Semiconductor

Part Name74ACT74 ON-Semiconductor
ON Semiconductor ON-Semiconductor
DescriptionDual D−Type Positive Edge−Triggered Flip−Flop


74ACT74 Datasheet PDF : 12 Pages
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MC74AC74, MC74ACT74
AC CHARACTERISTICS (For Figures and Waveforms See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74AC
74AC
Symbol
Parameter
VCC*
(V)
TA = +25°C
CL = 50 pF
TA = 40°C
to +85°C
CL = 50 pF
Unit
Fig.
No.
Min Typ Max Min Max
Maximum Clock
fmax
Frequency
3.3 100 125
95
5.0 140 160
125
MHz
33
Propagation Delay
tPLH
CDn or SDn to Qn or Qn
Propagation Delay
tPHL
CDn or SDn to Qn or Qn
Propagation Delay
tPLH
CPn to Qn or Qn
Propagation Delay
tPHL
CPn to Qn or Qn
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
3.3 5.0 8.0 12.5 4.0 13.0
5.0 3.5 6.0 9.0 3.0 10.0
ns
36
3.3 4.0 10.5 12.0 3.5 13.5
5.0 3.0 8.0 9.5 2.5 10.5
ns
36
3.3 4.5 8.0 13.5 4.0 16.0
5.0 3.5 6.0 10.0 3.0 10.5
ns
36
3.3 3.5 8.0 14.0 3.5 14.5
5.0 2.5 6.0 10.0 2.5 10.5
ns
36
AC OPERATING REQUIREMENTS
Symbol
Parameter
Set-up Time, HIGH or LOW
ts
Dn to CPn
Hold Time, HIGH or LOW
th
Dn to CPn
tw
CPn or CDn or SDn
Pulse Width
Recovery TIme
trec
CDn or SDn to CP
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
74AC
74AC
VCC*
(V)
TA = +25°C
CL = 50 pF
TA = 40°C
to +85°C
CL = 50 pF
Unit
Fig.
No.
Typ
Guaranteed Minimum
3.3 1.5
4.0
5.0 1.0
3.0
4.5
3.0
ns
39
3.3 2.0
0.5
5.0 1.5
0.5
0.5
0.5
ns
39
3.3 3.0
5.5
5.0 2.5
4.5
7.0
5.0
ns
36
3.3 2.5
0
5.0 2.0
0
0
0
ns
39
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Dual D−Type Positive Edge−Triggered Flip−Flop

  The MC74AC74/74ACT74 is a dual D−type flip−flop with Asynchronous Clear and Set inputs and complementary (Q,Q) outputs. Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input.
Asynchronous Inputs:
LOW input to SD(Set) sets Q to HIGH level
LOW input to CD(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CDand SDmakes both Q and QHIGH

Features
•Outputs Source/Sink 24 mA
•′ACT74 Has TTL Compatible Inputs
•Pb−Free Packages are Available

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