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74ACT74 View Datasheet(PDF) - ON Semiconductor

Part Name74ACT74 ON-Semiconductor
ON Semiconductor ON-Semiconductor
DescriptionDual D−Type Positive Edge−Triggered Flip−Flop


74ACT74 Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
MC74AC74, MC74ACT74
TRUTH TABLE (Each Half)
Inputs
Outputs
SD
CD
CP
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
H
H
H
H
H
L
H
H
L
L
H
H
H
L
X
Q0
Q0
NOTE:
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial;
= LOW-to-HIGH Clock Transition
Q0(Q0) = Previous Q(Q) before LOW-to-HIGH
Transition of Clock
Q1
Q1
SD1
CD1
D1 CP1
Q2
SD2
D2 CP2
Q2
CD2
Figure 2. Logic Symbol
SD
D
Q
CP
Q
CD
NOTE:
This diagram is provided only for the understanding of
logic operations and should not be used to estimate
propagation delays.
Figure 3. Logic Diagram
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
0.5 to +7.0
V
Vin
DC Input Voltage (Referenced to GND)
0.5 to VCC +0.5
V
Vout
DC Output Voltage (Referenced to GND)
0.5 to VCC +0.5
V
Iin
DC Input Current, per Pin
±20
mA
Iout
DC Output Sink/Source Current, per Pin
±50
mA
ICC
DC VCC or GND Current per Output Pin
±50
mA
Tstg
Storage Temperature
65 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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Dual D−Type Positive Edge−Triggered Flip−Flop

  The MC74AC74/74ACT74 is a dual D−type flip−flop with Asynchronous Clear and Set inputs and complementary (Q,Q) outputs. Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input.
Asynchronous Inputs:
LOW input to SD(Set) sets Q to HIGH level
LOW input to CD(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CDand SDmakes both Q and QHIGH

Features
•Outputs Source/Sink 24 mA
•′ACT74 Has TTL Compatible Inputs
•Pb−Free Packages are Available

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