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74ACT74 View Datasheet(PDF) - ON Semiconductor

Part Name74ACT74 ON-Semiconductor
ON Semiconductor ON-Semiconductor
DescriptionDual D−Type Positive Edge−Triggered Flip−Flop


74ACT74 Datasheet PDF : 12 Pages
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MC74AC74, MC74ACT74
Dual D−Type Positive
Edge−Triggered Flip−Flop
The MC74AC74/74ACT74 is a dual Dtype flipflop with
Asynchronous Clear and Set inputs and complementary (Q,Q)
outputs. Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at a voltage
level of the clock pulse and is not directly related to the transition time
of the positive-going pulse. After the Clock Pulse input threshold
voltage has been passed, the Data input is locked out and information
present will not be transferred to the outputs until the next rising edge
of the Clock Pulse input.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q HIGH
Features
Outputs Source/Sink 24 mA
ACT74 Has TTL Compatible Inputs
PbFree Packages are Available
VCC CD2 D2 CP2 SD2 Q2 Q2
14 13 12 11 10 9 8
D1 CD1 Q1
CP1 SD1 Q1
CP2 SD2 Q2
D2 CD2 Q2
http://onsemi.com
14
1
14
1
PDIP14
N SUFFIX
CASE 646
SOIC14
D SUFFIX
CASE 751A
14
1
TSSOP14
DT SUFFIX
CASE 948G
14
1
SOEIAJ14
M SUFFIX
CASE 965
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
1234567
CD1 D1 CP1 SD1 Q1 Q1 GND
Figure 1. Pinout: 14Lead Packages Conductors
(Top View)
PIN ASSIGNMENT
PIN
FUNCTION
D1, D2
CP1, CP2
CD1, CD2
SD1, SD2
Q1, Q1, Q2,
Q2
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
© Semiconductor Components Industries, LLC, 2006
1
October, 2006 Rev. 7
Publication Order Number:
MC74AC74/D
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Dual D−Type Positive Edge−Triggered Flip−Flop

  The MC74AC74/74ACT74 is a dual D−type flip−flop with Asynchronous Clear and Set inputs and complementary (Q,Q) outputs. Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input.
Asynchronous Inputs:
LOW input to SD(Set) sets Q to HIGH level
LOW input to CD(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CDand SDmakes both Q and QHIGH

Features
•Outputs Source/Sink 24 mA
•′ACT74 Has TTL Compatible Inputs
•Pb−Free Packages are Available

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