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74ACT74 View Datasheet(PDF) - ON Semiconductor

Part Name74ACT74 ON-Semiconductor
ON Semiconductor ON-Semiconductor
DescriptionDual D−Type Positive Edge−Triggered Flip−Flop


74ACT74 Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
MC74AC74, MC74ACT74
SOIC14
CASE 751A03
ISSUE H
14
1
T
SEATING
PLANE
A
8
BP 7 PL
0.25 (0.010) M B M
7
G
C
R X 45 _
F
D 14 PL
K
M
J
0.25 (0.010) M T B S A S
SOLDERING FOOTPRINT*
14X
0.58
7X
7.04
1
14X
1.52
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC
0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
10
Direct download click here
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Dual D−Type Positive Edge−Triggered Flip−Flop

  The MC74AC74/74ACT74 is a dual D−type flip−flop with Asynchronous Clear and Set inputs and complementary (Q,Q) outputs. Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input.
Asynchronous Inputs:
LOW input to SD(Set) sets Q to HIGH level
LOW input to CD(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CDand SDmakes both Q and QHIGH

Features
•Outputs Source/Sink 24 mA
•′ACT74 Has TTL Compatible Inputs
•Pb−Free Packages are Available

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