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6275 Просмотр технического описания (PDF) - Allegro MicroSystems

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6275 DABiC-IV, 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER Allegro
Allegro MicroSystems Allegro
6275 Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
6818
32-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C
CLOCK
50%
SERIAL
DATA IN
SERIAL
DATA OUT
A
B
DATA
50%
t p(CH-SQX)
50%
D
E
DATA
STROBE
50%
BLANKING
OUT N
LOW = ALL OUTPUTS ENABLED
t p(STH-QH)
t p(STH-QL)
90%
DATA
10%
Dwg. WP-029
BLANKING
OUT N
HIGH = ALL OUTPUTS BLANKED (DISABLED)
50%
t en(BQ)
t dis(BQ)
tr
DATA
10%
tf
90%
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) ......................................... 25 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) ............................................... 25 ns
C. Clock Pulse Width, tw(CH) ............................................... 50 ns
D. Time Between Clock Activation and Strobe, tsu(C) ....... 100 ns
E. Strobe Pulse Width, tw(STH) ............................................. 50 ns
NOTE – Timing is representative of a 10 MHz clock. Signifi-
cantly higher speeds are attainable.
Serial Data present at the input is transferred to the
shift register on the logic “0” to logic “1” transition of the
CLOCK input pulse. On succeeding CLOCK pulses, the
registers shift data information towards the SERIAL DATA
OUTPUT. The SERIAL DATA must appear at the input
prior to the rising edge of the CLOCK input waveform.
Dwg. WP-030
Information present at any register is transferred to
the respective latch when the STROBE is high (serial-to-
parallel conversion). The latches will continue to accept
new data as long as the STROBE is held high. Applica-
tions where the latches are bypassed (STROBE tied high)
will require that the BLANKING input be high during serial
data entry.
When the BLANKING input is high, the output source
drivers are disabled (OFF); the pnp active pull-down sink
drivers are ON. The information stored in the latches is
not affected by the BLANKING input. With the BLANK-
ING input low, the outputs are controlled by the state of
their respective latches.
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