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27C010 データシートの表示(PDF) - National ->Texas Instruments

27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM National-Semiconductor
National ->Texas Instruments National-Semiconductor
27C010 Datasheet PDF : 12 Pages
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Functional Description
The six modes of operation of the EPROM are listed in Ta-
ble I It should be noted that all inputs for the six modes are
at TTL levels The power supplies required are VCC and
VPP The VPP power supply must be at 12 75V during the
three programming modes and must be at 5V in the other
three modes The VCC power supply must be at 6 25V dur-
ing the three programming modes and at 5V in the other
three modes
Read Mode
The EPROM has two control functions both of which must
be logically active in order to obtain data at the outputs
Chip Enable (CE) is the power control and should be used
for device selection Output Enable (OE) is the output con-
trol and should be used to gate data to the output pins
independent of device selection Assuming that the ad-
dresses are stable address access time (tACC) is equal to
the delay from CE to output (tCE) Data is available at the
outputs tOE after the falling edge of OE assuming that CE
has been low and addresses have been stable for at least
tACC – tOE
Standby Mode
The EPROM has a standby mode which reduces the active
power dissipation by over 99% from 165 mW to 0 55 mW
The EPROM is placed in the standby mode by applying a
CMOS high signal to the CE input When in standby mode
the outputs are in a high impedance state independent of
the OE input
Output Disable
The EPROM is placed in output disable by applying a TTL
high signal to the OE input When in output disable all cir-
cuitry is enabled except the outputs are in a high imped-
ance state (TRI-STATE)
Output OR-Tying
Because the EPROM is usually used in larger memory ar-
rays National has provided a 2-line control function that
accommodates this use of multiple memory connections
The 2-line control function allows for
a) the lowest possible memory power dissipation and
b) complete assurance that output bus contention will not
To most efficiently use these two control lines it is recom-
mended that CE be decoded and used as the primary de-
vice selecting function while OE be made a common con-
nection to all devices in the array and connected to the
READ line from the system control bus This assures that all
deselected memory devices are in their low power standby
modes and that the output pins are active only when data is
desired from a particular memory device
CAUTION Exceeding 14V on the VPP or A9 pin will damage
Initially and after each erasure all bits of the EPROM are in
the ‘‘1’s’’ state Data is introduced by selectively program-
ming ‘‘0’s’’ into the desired bit locations Although only
‘‘0’s’’ will be programmed both ‘‘1’s’’ and ‘‘0’s’’ can be pre-
sented in the data word The only way to change a ‘‘0’’ to a
‘‘1’’ is by ultraviolet light erasure
The EPROM is in the programming mode when the VPP
power supply is at 12 75V and OE is at VIH It is required
that at least a 0 1 mF capacitor be placed across VPP VCC
to ground to suppress spurious voltage transients which
may damage the device The data to be programmed is
applied 8 bits in parallel to the data output pins The levels
required for the address and data inputs are TTL
When the address and data are stable an active low TTL
program pulse is applied to the PGM input A program pulse
must be applied at each address location to be pro-
grammed The EPROM is programmed with the Fast Pro-
gramming Algorithm shown in Figure 1 Each Address is
programmed with a series of 100 ms pulses until it verifies
good up to a maximum of 25 pulses Most memory cells will
program with a single 100 ms pulse
The EPROM must not be programmed with a DC signal ap-
plied to the PGM input
Programming multiple EPROM in parallel with the same
data can be easily accomplished due to the simplicity of the
programming requirements Like inputs of the parallel
EPROM may be connected together when they are pro-
grammed with the same data A low level TTL pulse applied
to the PGM input programs the paralleled EPROM
Program Inhibit
Programming multiple EPROM’s in parallel with different
data is also easily accomplished Except for CE all like in-
puts (including OE and PGM) of the parallel EPROM may be
common A TTL low level program pulse applied to an
EPROM’s PGM input with CE at VIL and VPP at 12 75V will
program that EPROM A TTL high level CE input inhibits the
other EPROM’s from being programmed
Program Verify
A verify should be performed on the programmed bits to
determine whether they were correctly programmed The
verify may be performed with VPP at 12 75V VPP must be at
VCC except during programming and program verify
Opaque labels should be placed over the EPROM window
to prevent unintentional erasure Covering the window will
also prevent temporary functional failure due to the genera-
tion of photo currents
The EPROM has a manufacturer’s indentification code to
aid in programming When the device is inserted in an
EPROM programmer socket the programmer reads the
code and then automatically calls up the specific program-
ming algorithm for the part This automatic programming
control is only possible with programmers which have the
capability of reading the code
The Manufacturer’s Identification code shown in Table II
specifically identifies the manufacturer and device type The
code for the NM27C010 is ‘‘8F86’’ where ‘‘8F’’ designates
that it is made by National Semiconductor and ‘‘86’’ desig-
nates a 1 Megabit (128K c 8) part
The code is accessed by applying 12V g0 5V to address
pin A9 Addresses A1–A8 A10–A16 and all control pins
are held at VIL Address pin A0 is held at VIL for the manu-
facturer’s code and held at VIH for the device code The
code is read on the eight data pins O0–07 Proper code
access is only guaranteed at 25 C g 5 C
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