FW21555BA View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

FW21555BA

Non-Transparent PCI-to-PCI Bridge

Intel 

Non-Transparent PPB

Table 1.

21555 and PPB Feature Comparison

Feature

Transaction

forwarding

Address decoding

Address

translation

Configuration

Run-time resources

Clocks

Secondary bus

central functions

21555

PCI-to-PCI Bridge

Adheres to PPB ordering rules.

Adheres to PPB ordering rules.

Uses posted writes and delayed

transactions.

Uses posted writes and delayed transactions.

Adheres to PPB transaction error and

parity error guidelines, although some

errors may be reported differently.

Adheres to PPB transaction error and parity

error guidelines.

Base address registers are used to

define independent downstream and

upstream forwarding windows.

Inverse decoding is only used for

upstream transactions above the

4 GB boundary.

PPB base and limit address registers are

used to define downstream forwarding

windows.

Inverse decoding for upstream forwarding.

Supported for both memory and I/O No translation, a flat address model is

transactions.

assumed.

Downstream devices are not visible

to host.

Downstream devices are visible to host.

Does not require hierarchical

configuration code (Type 0

configuration header).

Requires hierarchical configuration code

(Type 1 configuration header).

Does not respond to Type 1

configuration transactions.

Supports configuration access from

the secondary bus.

Implements separate set of

configuration registers for the

secondary interface.

Forwards and converts Type 1 configuration

transactions.

Does not support configuration access from

the secondary bus. Same set of

configuration registers is used to control both

primary and secondary interfaces.

Includes features such as doorbell

interrupts, I2O message unit, and so

on, that must be managed by the

device driver.

Typically has only configuration registers; no

device driver is required.

Generates secondary bus clock

output.

Asynchronous secondary clock input

is also supported.

Generates one or more secondary bus clock

outputs.

Implements secondary bus arbiter.

This function can be disabled.

Implements secondary bus arbiter.

Drives secondary bus AD, C/BE#,

and PAR during reset. This function

can be disabled.

Drives secondary bus AD, C/BE#, and PAR

during reset.

Datasheet

7

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