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M2201VDW6 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
M2201VDW6
ST-Microelectronics
STMicroelectronics ST-Microelectronics
M2201VDW6 Datasheet PDF : 15 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
M2201
Read Operation
Byte Read. The master sends a START condition
followed by seven bits of address and the RW bit
(set to ’1’). The M2201 acknowledges it and outputs
the corresponding data byte. The read operation
is terminated by a STOP condition issued by the
master (instead of the ACK bit).
Sequential Read. The master sends a START
condition followed by seven bits of address and the
RW bit (set to ’1’). The M2201 acknowledges it and
outputs the corresponding data byte. The master
does acknowledge this byte and reads the next
data byte (at address + 1). The read operation is
terminated by a STOP condition issued by the
master (instead of the ACK bit). The output data is
from consecutive byte addresses, with the internal
byte address counter automatically incremented
after each byte output. After a count of the last
memory address, the address counter will ’roll-
over to address ’00’ and the memory will continue
to output data.
Acknowledge in Read Mode. In all read modes
the M2201 waits for an acknowledge during the 9th
bit time. If the master does not pull the SDA line low
during this time, the M2201 terminates the data
transfer and switches to a standby state.
Figure 8. Write Modes Sequences with Write Control = 1 (M2201 and M2201V)
WC
BYTE WRITE
ACK
NO ACK
BYTE ADDR
DATA IN
R/W = 0
WC
PAGE WRITE
ACK
NO ACK
BYTE ADDR
DATA IN 1
R/W = 0
NO ACK
NO ACK
DATA IN 4
AI01324
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