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M2201B6TR View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
M2201B6TR
ST-Microelectronics
STMicroelectronics ST-Microelectronics
M2201B6TR Datasheet PDF : 15 Pages
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M2201
Byte Write. In the Byte Write mode the master
sends one data byte, which is acknowledged by the
memory. The master then terminates the transfer
by generating a STOP condition.
Page Write. The Page Write mode allows up to 4
bytes to be written in a single write cycle, provided
that they are all located in the same ’row’ in the
memory: that is the 5 most significant memory
address bits (A6-A2) are the same. The master
sends from one up to four bytes of data, which are
each acknowledged by the memory. After each
byte is transfered, the internal byte address counter
(2 least significant bits only) is incremented. The
transfer is terminated by the master generating a
STOP condition. Care must be taken to avoid ad-
dress counter ’roll-over’ which could result in data
being overwritten.
It must be noticed that, for any write mode, the
generation by the master of the STOP condition
starts the internal memory program cycle. All inputs
are disabled until the completion of this cycle and
the memory will not respond to any request.
Minimizing System Delays by Polling On ACK.
During the internal write cycle, the memory discon-
nects itself from the bus in order to copy the data
from the internal latches to the memory cells. The
maximum value of the write time (tW) is given in the
AC Characteristics table, since the typical time is
shorter, the time seen by the system may be re-
Figure 6. I2C Bus Protocol
SCL
SDA
START
CONDITION
SDA
SDA
INPUT CHANGE
STOP
CONDITION
SCL
SDA
1
2
3
MSB
START
CONDITION
SCL
SDA
1
2
3
MSB
7
8
9
ACK
7
8
9
ACK
STOP
CONDITION
AI00792
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