BR9010 View Datasheet(PDF) - ROHM Semiconductor

Part Name

Description

Manufacturer

BR9010

1, 2, and 4k bit EEPROMs for direct connection to serial ports

ROHM Semiconductor 

Memory ICs

BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F /

BR9040 / BR9040F

1) During input in the write mode, CS must be LOW, but once writing starts, CS may be either HIGH or LOW.

However, if CS and WC share the same connection, both CS and WC should be set to LOW during writing oper-

ations.

(If the WC pin is set to HIGH during a writing operation, writing will be forcibly interrupted at that point. If this hap-

pens, the data for that address may be lost, in which case it should be rewritten to that address.)

2) Following input of a write command, CS goes HIGH. If CS is then set to LOW, data will be received from SK and

DI, because the command reception status has been entered.

If CS remains LOW following command input, however, without first going HIGH, command input will be can-

celed until CS is set to HIGH.

3) Starting from the rising edge of the 32nd clock, the R / B pin goes LOW after RSV has elapsed.

4) The R / B pin is LOW during writing operations. (Following the rising edge of SK after the last data D15 has been

read, the internal timer circuit is activated, and writing of data in the memory cell is automatically completed dur-

ing tE / W.) At this point, SK input may be either HIGH or LOW during tE / W.

5) Following input of a write command, if CS falls while SK is LOW, the R / B status can be displayed from the DO

pin. (See the section on READY / BUSY states.)

(6) READY / BUSY display (R / B pin and DO pin)

1) This display outputs the internal status signal; the R / B pin outputs the HIGH or LOW status at all times. The dis-

play can also be output from the DO pin. Following completion of the writing command, if CS falls while SK is

LOW, either HIGH or LOW is output. (The display can also be output without using the R / B pin, leaving it open.)

2) When writing data to a memory cell, the READY / BUSY display is output from the rise of the 32nd clock pulse of

the SK signal after tSV, from the R / B pin.

R / B display = LOW: writing in progress

(The internal timer circuit is activated, and after the tE / W timing has been created, the timer circuit stops automati-

cally. Writing of data to the memory cell is done during the tE / W timing, during which time other commands can-

not be received.)

R / B display = HIGH: command standby state

(Writing of data to the memory cell has been completed and the next command can be received.)

SK

Clock

CS

DI

DO

R/B

READY

Write command

HIGH-Z

tPD

BUSY

tOZ

READY

HIGH-Z

BUSY READY

Fig.8 R / B status output timing

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