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ST24FC21B1TR View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
ST24FC21B1TR Datasheet PDF : 22 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Table 7. AC Characteristics, I2C Bidirectional Mode for Clock Frequency = 400kHz
(TA = –40 to 85 °C; VCC = 3.6 to 5.5V or VCC = 2.5 to 5.5V)
Symbol
tCH1CH2 (1)
tCL1CL2 (1)
tDH1DH2 (1)
tDL1DL2 (1)
tCHDX (2)
Alt
tR
tF
tR
tF
tSU:STA
Parameter
Clock Rise Time
Clock Fall Time
SDA Rise Time
SDA Fall Time
Clock High to Input Transition
Min
Max
300
300
20
300
20
300
600
tCHCL
tHIGH
Clock Pulse Width High
600
tDLCL
tHD:STA
Input Low to Clock Low (START)
600
tCLDX
tHD:DAT
Clock Low to Input Transition
0
tCLCH
tLOW
Clock Pulse Width Low
1.3
tDXCX
tSU:DAT
Input Transition to Clock Transition
100
tCHDH
tSU:STO Clock High to Input High (STOP)
600
tDHDL
tCLQV
tBUF
Input High to Input Low (Bus Free)
tAA
Clock Low to Data Out Valid
1.3
200
900
tCLQX
tDH
Clock Low to Data Out Transition
200
fC
fSCL
Clock Frequency
400
tW
tWR
Write Time
10
Notes: 1. Sampled only, not 100% tested.
2. For a reSTART condition, or following a write cycle.
Unit
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
µs
ns
ns
kHz
ms
I2C Bus Background
The ST24xy21 supports the I2C protocol. This pro-
tocol defines any device that sends data onto the
bus as a transmitter and any device that reads the
data as a receiver. The device that controls the data
transfer is known as the master and the other as
the slave. The master will always initiate a data
transfer and will provide the serial clock for syn-
chronisation. The ST24xy21 are always slave de-
vices in all communications.
Start Condition. START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the ST24xy21 con-
tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
The ST24LC21B, ST24LW21, ST24FC21 and
ST24FW21 are not executing a START condition if
this START condition happens at any time inside a
byte. The ST24FC21B executes a START condi-
tion when this START condition happens at any
time inside a byte.
Stop Condition. STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the ST24xy21 and
the bus master. A STOP condition at the end of a
Read command (after the No ACK) forces the
standby state. A STOP condition at the end of a
Write command triggers the internal EEPROM
write cycle.
The ST24LC21B, ST24LW21, ST24FC21 and
ST24FW21 are not executing a STOP condition if
this STOP condition happens at any time inside a
byte. The ST24FC21B executes a STOP condition
when this STOP condition happens at any time
inside a byte.
Acknowledge Bit (ACK). An acknowledge signal
is used to indicate a successfull data transfer. The
bus transmitter, either master or slave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledge the receipt of the 8 bits of
data.
Data Input. During data input, the ST24xy21 sam-
ple the SDA bus signal on the rising edge of the
clock SCL. Note that for correct device operation
10/22
 

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