ST93C47CM6013TR View Datasheet(PDF) - STMicroelectronics
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ST93C47CM6013TR Datasheet PDF : 13 Pages
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Figure 8. WRAL Sequence
ST93C46A/46C/46T, ST93C47C/47T
WRITE
S
ALL
D
1 0 0 0 1 Xn X0 Dn
CHECK
STATUS
D0
Q
ADDR
OP
CODE
Note: 1. Xn: n = 3 for x16 org. and 4 for x8 org.
DATA IN
BUSY
READY
AI00880C
READY/BUSY Status
During every programming cycle (after a WRITE,
ERASE, WRAL or ERAL instruction) the Data Out-
put (Q) indicates the Ready/Busy status of the
memory when the Chip Select is driven High. Once
the ST93C46 is Ready, the Data Output is set to ’1’
until a new start bit is decoded or the Chip Select
is brought Low.
COMMON I/O OPERATION
The Data Output (Q) and Data Input (D) signals can
be connected together, through a current limiting
resistor, to form a common, one wire data bus.
Some precautions must be taken when operating
the memory with this connection, mostly to prevent
a short circuit between the last entered address bit
(A0) and the first data bit output by Q. The reader
should refer to the SGS-THOMSON application
note ”MICROWIRE EEPROM Common I/O Opera-
tion”.
DIFFERENCES BETWEEN ST93C46A AND
ST93C46C
The ST93C46C is an enhanced version of the
ST93C46A and offers the following extra features:
– Enhanced ESD voltage
– Functional security filtering glitches on the
clock input (C).
Refer to Table 2 (Absolute Maximum Ratings) for
more about ESD limits. The following description
will detail the Clock pulses counter (available only
on the ST93C46C).
In a normal environment, the ST93C46 is expected
to receive the exact amount of data on the D input,
that is the exact amount of clock pulses on the C
input.
In a noisy environment, the amount of pulses re-
ceived (on the clock input C) may be greater than
the clock pulsesdelivered by the Master (Microcon-
troller) driving the ST93C46C. In such a case, a
part of the instruction is delayed by one bit (see
Figure 9), and it may induce an erroneous write of
data at a wrong address.
The ST93C46C has an on-board counter which
counts the clock pulses from the Start bit until the
falling edge of the Chip Select signal. For the
WRITE instructions, the number of clock pulses
incoming to the counter must be exactly 18 (with
the Organisation by 8) from the Start bit to the
falling edge of Chip Select signal (1 Start bit + 2 bits
of Op-code + 7 bits of Address + 8 bits of Data =
18): if so, the ST93C46C executes the WRITE
instruction; if the number of clock pulses is not
equal to 18, the instruction will not be executed
(and data will not be corrupted).
In the same way, when the Organisation by 16 is
selected, the number of clock pulses incoming to
the counter must be exactly 25 (1 Start bit + 2 bits
of Op-code + 6 bits of Address + 16 bits of Data =
25) from the Start bit to the falling edge of Chip
Select signal: if so, the ST93C46C executes the
WRITE instruction; if the number of clock pulses is
not equal to 25, the instruction will not be executed
(and data will not be corrupted). The clock pulse
counter is active only on ERASE and WRITE in-
structions (WRITE, ERASE, ERAL, WRALL).
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