ST93C47TM1TR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST93C47TM1TR Datasheet PDF : 13 Pages
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ST93C46A/46C/46T, ST93C47C/47T
MEMORY ORGANIZATION
The ST93C46 is organised as 128 bytes x 8 bits or
64 words x 16 bits. If the ORG input is left uncon-
nected (or connected to VCC) the x16 organization
is selected, when ORG is connected to Ground
(VSS) the x8 organization is selected. When the
ST93C46 is in standby mode, the ORG input
should be unconnected or set to either VSS or VCC
in order to get minimum power consumption. Any
voltage between VSS and VCC applied to ORG may
increase the standby current value.
POWER-ON DATA PROTECTION
During power-up, A Power On Reset sequence is
run in order to reset all internal programming cir-
cuitry and the device is set in the Write Disable
mode. When VCC reaches its functional value, the
device is properlyreset (in the Write Disable mode)
and is ready to decode and execute an incoming
instruction.
INSTRUCTIONS
The ST93C46 has seven instructions, as shown in
Table 6. Each instruction is preceded by the rising
edge of the signal applied on the S input (assuming
that the clock C is low), followed by a ’1’ read on D
input during the rising edge of the clock C. The
op-codes of the instructions are made up of the 2
followingbits. Some instructions useonly these first
two bits, others use also the first two bits of the
address to define the op-code. The op-code is
followed by an address for the byte/word which is
made up of six bits for the x16 organization or
seven bits for the x8 organization.
The ST93C46 is fabricated in CMOS technology
and is therefore able to run from zero Hz (static
input signals) up to the maximum ratings (specified
in Table 5).
Read
The Read instruction (READ) outputs serial data
on the Data Output (Q). When a READ instruction
is received, the instruction and address are de-
coded and the data from the memory is transferred
into an output shiftregister. A dummy ’0’ bit is output
first followed by the 8 bit byte or the 16 bit word with
the MSB first. Output data changes are triggered
by the Low to High transition of the Clock (C). The
ST93C46 will automatically increment the address
and will clock out the next byte/word as long as the
Chip Select input (S) is held High. In this case the
dummy ’0’ bit is NOT output between bytes/words
and a continuous stream of data can be read.
Erase/Write Enable and Disable
The Erase/Write Enable instruction (EWEN)
authorizesthe following Erase/Write instructions to
be executed, the Erase/Write Disable instruction
(EWDS) freezes the execution of the following
Erase/Write instructions. When power is first ap-
plied to the ST93C46, Erase/Write is inhibited.
When the EWEN instruction is executed, Write
instructions remain enabled until an Erase/Write
Disable instruction (EWDS) is executed or VCC falls
below the power-on reset threshold. To protect the
memory contents from accidental corruption, it is
advisable to issue the EWDS instruction after every
write cycle.
The READ instruction is not affected by the EWEN
or EWDS instructions.
Table 6. Instruction Set
Instruction
Description
READ Read Data from Memory
WRITE Write Data to Memory
EWEN Erase/Write Enable
EWDS Erase/Write Disable
ERASE Erase Byte or Word
ERAL
Erase All Memory
WRAL Write All Memory with same Data
Note: X = don’t care bit.
Op-Code
10
01
00
00
11
00
00
x8 Org
Address
(ORG = 0)
A6-A0
A6-A0
11XXXXX
00XXXXX
A6-A0
10XXXXX
01XXXXX
Data
Q7-Q0
D7-D0
D7-D0
x16 Org
Address
(ORG = 1)
A5-A0
A5-A0
11XXXX
00XXXX
A5-A0
10XXXX
01XXXX
Data
Q15-Q0
D15-D0
D15-D0
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