ST93C47CM6013TR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST93C47CM6013TR Datasheet PDF : 13 Pages
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Figure 5. Synchronous Timing, Read or Write
ST93C46A/46C/46T, ST93C47C/47T
C
S
tDVCH
tCHDX
D
An
A0
Hi-Z
Q
tCHQL
tCHQV
Q15/Q7
tCLSL
tSLSH
tSLQZ
Q0
ADDRESS INPUT
C
S
tDVCH
D
An
Hi-Z
Q
tCHDX
A0/D0
ADDRESS/DATA INPUT
DATA OUTPUT
AI00820C
tSLCH
tCLSL
tSLSH
tSHQV tSLQZ
BUSY
READY
tW
WRITE CYCLE
AI01429
DESCRIPTION (cont’d)
counter automatically rolls over to ’00’ when the
highest address is reached.
Programming is internally self-timed (the external
clock signal on C input may be disconnected or left
running after the start of a Write cycle) and does
not require an erase cycle prior to the Write instruc-
tion. The Write instruction writes 8 or 16 bits at one
time into one of the 128 bytes or 64 words. After
the start of the programming cycle a Busy/Ready
signal is available on the Data output (Q) when
Chip Select (S) is High.
An internal feature of the ST93C46 provides
Power-on Data Protection by inhibiting any opera-
tion when the Supply is too low. The design of the
ST93C46 and the High Endurance CMOS technol-
ogy used for its fabrication give an Erase/Write
cycle Endurance of 1,000,000 cycles and a data
retention of 40 years.
The DU (Don’t Use) pin does not affect the function
of the memory and it is reserved for use by SGS-
THOMSON during test sequences.The pin may be
left unconnected or may be connected to VCC or
VSS. Direct connection of DU to VSS is recom-
mended for the lowest standby power consump-
tion.
5/13
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