ST93C47CB6TR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST93C47CB6TR

1K (64 x 16 or 128 x 8) SERIAL MICROWIRE EEPROM

STMicroelectronics 

ST93C46A/46C/46T, ST93C47C/47T

Table 5. AC Characteristics

(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V or 3V to 5.5V)

Symbol Alt

Parameter

Test Condition

Min

Max

Unit

tSHCH

tCSS Chip Select High to Clock High

50

ns

tCLSH

tDVCH

tSKS Clock Low to Chip Select High

tDIS Input Valid to Clock High

100

ns

100

ns

Temp. Range: grade 1 100

ns

tCHDX

tDIH Clock High to Input Transition

Temp. Range:

grades 3, 6

200

ns

tCHQL

tCHQV

tPD0 Clock High to Output Low

tPD1 Clock High to Output Valid

500

ns

500

ns

tCLSL

tCSH Clock Low to Chip Select Low

0

ns

tSLCH

Chip Select Low to Clock High

250

ns

tSLSH

tCS Chip Select Low to Chip Select High

Note 1

250

ns

tSHQV

tSLQZ

tSV Chip Select High to Output Valid

tDF Chip Select Low to Output Hi-Z

ST93C46A

ST93C46C, 47C

500

ns

300

ns

200

ns

tCHCL

tSKH Clock High to Clock Low

Note 2

250

ns

tCLCH

tSKL Clock Low to Clock High

Note 2

250

ns

tW

tWP Erase/Write Cycle time

10

ms

fC

fSK Clock Frequency

0

1

MHz

Notes: 1. Chip Select must be brought low for a minimum of 250 ns (tSLSH) between consecutive instruction cycles.

2. The Clock frequency specification calls for a minimum clock period of 1 µs, therefore the sum of the timings tCHCL + tCLCH

must be greater or equal to 1 µs. For example, if tCHCL is 250 ns, then tCLCH must be at least 750 ns.

Figure 4. Synchronous Timing, Start and Op-Code Input

tCLSH

tCHCL

C

tSHCH

tCLCH

S

tDVCH

tCHDX

D

START

OP CODE

OP CODE

START

OP CODE INPUT

AI01428

4/13

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