Electronic component search and free download site.
Transistors,MosFET ,Diode,Integrated circuits

89LPC933 View Datasheet(PDF) - NXP Semiconductors.

Part Name
Description
Manufacturer
89LPC933 Datasheet PDF : 77 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
NXP Semiconductors
P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
Table 4. Pin description …continued
Symbol
Pin
Type Description
TSSOP28, HVQFN28
PLCC28
P1.0 to P1.7
I/O, I [1] Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type,
except for three pins as noted below. During reset Port 1 latches are
configured in the input only mode with the internal pull-up disabled. The
operation of the configurable Port 1 pins as inputs and outputs depends
upon the port configuration selected. Each of the configurable port pins
are programmed independently. Refer to Section 8.13.1 “Port
configurations” and Table 11 “Static characteristics” for details. P1.2 and
P1.3 are open drain when used as outputs. P1.5 is input only.
All pins have Schmitt trigger inputs.
Port 1 also provides various special functions as described below:
P1.0/TXD 18
14
I/O P1.0 — Port 1 bit 0.
O
TXD — Transmitter output for the serial port.
P1.1/RXD 17
13
I/O P1.1 — Port 1 bit 1.
I
RXD — Receiver input for the serial port.
P1.2/T0/SCL 12
8
I/O P1.2 — Port 1 bit 2 (open-drain when used as output).
I/O T0 — Timer/counter 0 external count input or overflow output (open-drain
when used as output).
I/O
SCL — I2C serial clock input/output.
P1.3/INT0/ 11
7
SDA
I/O P1.3 — Port 1 bit 3 (open-drain when used as output).
I
INT0 — External interrupt 0 input.
I/O
SDA — I2C serial data input/output.
P1.4/INT1 10
6
I
P1.4 — Port 1 bit 4.
I
INT1 — External interrupt 1 input.
P1.5/RST 6
2
I
P1.5 — Port 1 bit 5 (input only).
I
RST — External reset input during power-on or if selected via UCFG1.
When functioning as a reset input, a LOW on this pin resets the
microcontroller, causing I/O ports and peripherals to take on their default
states, and the processor begins execution at address 0. Also used during
a power-on sequence to force ISP mode. When using an oscillator
frequency above 12 MHz, the reset input function of P1.5 must be
enabled. An external circuit is required to hold the device in reset at
power-up until VDD has reached its specified level. When system
power is removed VDD will fall below the minimum specified
operating voltage. When using an oscillator frequency above
12 MHz, in some applications, an external brownout detect circuit
may be required to hold the device in reset when VDD falls below the
minimum specified operating voltage.
P1.6/OCB 5
1
I/O P1.6 — Port 1 bit 6.
O
OCB — Output Compare B. (P89LPC935/936)
P1.7/OCC/ 4
AD00
28
I/O P1.7 — Port 1 bit 7.
O
OCC — Output Compare C. (P89LPC935/936)
I
AD00 — ADC0 channel 0 analog input. (P89LPC935/936)
P89LPC933_934_935_936
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 January 2011
© NXP B.V. 2011. All rights reserved.
8 of 77
Direct download click here

 

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]