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89LPC933 View Datasheet(PDF) - NXP Semiconductors.

Part NameDescriptionManufacturer
89LPC933 8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCs NXP
NXP Semiconductors. NXP
89LPC933 Datasheet PDF : 77 Pages
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NXP Semiconductors
P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
These external interrupts can be programmed to be level-triggered or edge-triggered by
setting or clearing bit IT1 or IT0 in register TCON.
In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle
and a LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an
interrupt request.
If an external interrupt is enabled when the P89LPC933/934/935/936 is put into
Power-down or Idle mode, the interrupt will cause the processor to wake-up and resume
operation. Refer to Section 8.15 “Power reduction modes” for details.
RTCF
ERTC
(RTCCON.1)
WDOVF
EEIF(2)
ENADCI0(2)
ADCI0(2)
ENADCI1
ADCI1
ENBI0(2)
BNDI0(2)
ENBI1
BNDI1
EADEE (P89LPC935)
EAD (P89LPC933/934)
IE0
EX0
IE1
EX1
BOF
EBO
KBIF
EKBI
EWDRT
CMF2
CMF1
EC
EA (IE0.7)
TF0
ET0
TF1
ET1
TI & RI/RI
ES/ESR
TI
EST
SI
EI2C
SPIF
ESPI
any CCU interrupt(1)
ECCU
(1) See Section 8.19 “CCU (P89LPC935/936)”
(2) P89LPC935/936
Fig 9. Interrupt sources, interrupt enables, and power-down wake-up sources
wake-up
(if in power-down)
interrupt
to CPU
002aab081
P89LPC933_934_935_936
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 12 January 2011
© NXP B.V. 2011. All rights reserved.
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