89LPC933 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
89LPC933 Datasheet PDF : 77 Pages
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Table 5. Special function registers - P89LPC933/934 …continued
* indicates SFRs that are bit addressable.
Name
Description
SFR Bit functions and addresses
addr. MSB
LSB
Reset value
Hex Binary
WDL
Watchdog load
C1H
FF
1111 1111
WFEED1 Watchdog feed 1
C2H
WFEED2 Watchdog feed 2
C3H
[1] Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise specified, ones should not be written to these bits since they may be used for other
purposes in future derivatives. The reset values shown for these bits are logic 0s although they are unknown when read.
[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
[3] All ports are in input only (high-impedance) state after power-up.
[4] The RSTSRC register reflects the cause of the P89LPC933/934/935/936 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset
value is xx11 0000.
[5] The only reset source that affects these SFRs is power-on reset.
[6] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
[7] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.
Other resets will not affect WDTOF.
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