ADP5051
I2C INTERFACE TIMING DIAGRAMS
Figure 57 shows the timing diagram for the I2C write operation.
Figure 58 shows the timing diagram for the I2C read operation.
Data Sheet
Use the subaddress to select one of the user registers in the
ADP5051. The ADP5051 sends data to and from the register
specified by the subaddress.
SCL
SDA
A6 A5 A4 A3 A2 A1 A0 R/W
10010000
CHIP ADDRESS
A7 A6 A5 A4 A3 A2 A1 A0
SUBADDRESS
D7 D6 D5 D4 D3 D2 D1 D0
WRITE DATA
OUTPUT BY PROCESSOR
OUTPUT BY ADP5051
NOTES
1. MAXIMUM SCL FREQUENCY IS 400kHz.
2. NO RESPONSE TO GENERAL CALLS.
Figure 57. I2C Write to Register
SCL
SDA
A6 A5 A4 A3 A2 A1 A0 R/W
10010000
CHIP ADDRESS
A7 A6 A5 A4 A3 A2 A1 A0
SUBADDRESS
A6 A5 A4 A3 A2 A1 A0 R/W
10010001
CHIP ADDRESS
D7 D6 D5 D4 D3 D2 D1 D0
READ DATA
OUTPUT BY PROCESSOR
OUTPUT BY ADP5051
NOTES
1. MAXIMUM SCL FREQUENCY IS 400kHz.
2. NO RESPONSE TO GENERAL CALLS.
Figure 58. I2C Read from Register
Rev. B | Page 30 of 55