ADP5051 View Datasheet(PDF) - Analog Devices
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ADP5051 Datasheet PDF : 55 Pages
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Data Sheet
The reset output asserts when the monitored rail is below the
threshold (VTH) and when WDI is not serviced within the
watchdog timeout period (tWD). The RSTO pin remains asserted
for the duration of the reset active timeout period (tRP) after VCC
rises above the reset threshold or after the watchdog timer times
out. There are four options for the reset active timeout period
(tRP) that are available via the factory fuse: 1.4 ms, 28 ms, 200 ms
(default), or 1600 ms. Figure 51 illustrates the behavior of the
RSTO output, assuming that VOUT2 is selected as the rail to be
monitored, and it supplies the external pull-up connected to the
RSTO output.
VOUT2
VOUT2
1V
0V
RSTO
VOUT2
0V
VTH
tRP
VTH
tRD
Figure 51. Reset Timing Diagram
The ADP5051 has a dedicated sensing input pin (VTH) to
monitor the supply rail. The reset threshold at the VTH input is
typically 0.5 V. To monitor a voltage greater than 0.5 V, connect
a resistor divider network to the device.
Do not allow the VTH input to float or to be grounded. Instead,
connect the VTH input to a supply voltage greater than its
specified threshold voltage (VTH). Add a small capacitor on the
VTH input to improve the noise rejection and prevent false reset
generation.
When monitoring the input voltage, if the selected voltage falls
below the UVLO level, the reset output (RSTO) asserts low with
the delay time (tRD). The reset output is then kept low to restart
the processor.
Watchdog Input
The ADP5051 features a watchdog timer that monitors
microprocessor activity. A timer circuit is cleared with every
low to high or high to low logic transition on the watchdog
input pin (WDI), which detects pulses as short as 80 ns. If the
timer proceeds through the preset watchdog timeout period (tWD),
reset is asserted. The microprocessor is required to toggle the WDI
pin to avoid being reset. Therefore, failure of the microprocessor to
toggle the WDI pin within the timeout period indicates a code
execution error, and the reset pulse generated restarts the
microprocessor in a known state. Four options are available for
the watchdog timeout period via the factory fuse: 6.3 ms, 102 ms,
1600 ms (default), or 25.6 sec.
ADP5051
In addition to the logic transition on the WDI pin, the watchdog
timer is also cleared by a reset assertion due to an undervoltage
condition on VOUT2. When a reset is asserted, the watchdog
timer clears, and the timer does not begin counting again until
reset is deasserted. Disable the watchdog timer by leaving the
WDI pin floating or by three-stating the WDI driver. Figure 52
shows the watchdog timing diagram.
VOUT2
RSTO
VOUT2
1V
0V
VOUT2
0V
WDI
VOUT2
0V
VTH
tRP
tWD
tRP
Figure 52. Watchdog Timing Diagram
Manual Reset Input
The ADP5051 features a manual reset input (MR pin, active low)
with two operation modes: processor manual reset mode or
power on/off switch mode. The default setting is the processor
manual reset mode; however, MR operation mode selection can
be configured by factory fuse.
The MR input has an internal 55 kΩ pull-up resistor so that the
input remains high when unconnected. To generate a reset, connect
an external push-button switch between MR and ground. Noise
immunity is provided on the MR input, and fast, negative going
transients of up to 100 ns (typical) are ignored. A 0.1 µF capacitor
between MR and ground provides additional noise immunity.
Processor Manual Reset Mode
In processor manual reset mode, when MR is driven low, the
reset output is asserted. When MR transitions from low to high, the
reset remains asserted for the duration of the reset active timeout
period (tRP) before deasserting. Figure 53 shows the behavior of
the MR pin in processor manual reset mode.
VCC
VRT
VRT
tRP
tRP
RSTO
MR
MR EXTERNALLY
DRIVEN LOW
Figure 53. MR Timing Diagram in Processor Reset Mode
Rev. B | Page 27 of 55
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