ADP5051 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADP5051 Datasheet PDF : 55 Pages
| |||
ADP5051
Data Sheet
For the fixed output settings, the feedback resistor divider is
built into the ADP5051, and the feedback pin (FBx) must be
tied directly to the output. Each buck regulator channel can be
programmed for a specific output voltage range using the VIDx
bits in Register 2 to Register 4. Table 10 lists the fixed output
voltage ranges configured by the VIDx bits.
Table 10. Fixed Output Voltage Ranges Set by the VIDx Bits
Channel Fixed Output Voltage Range Set by the VIDx Bits
Channel 1 0.85 V to 1.6 V in 25 mV steps
Channel 2 3.3 V to 5.0 V in 300 mV or 200 mV steps
Channel 3 1.2 V to 1.8 V in 100 mV steps
Channel 4 2.5 V to 5.5 V in 100 mV steps
The output range can also be programmed by factory fuse. If
a different output voltage range is required, contact your local
Analog Devices, Inc., sales or distribution representative.
DYNAMIC VOLTAGE SCALING (DVS)
The ADP5051 provides a dynamic voltage scaling (DVS) function
for Channel 1 and Channel 4; these outputs can be programmed
in real-time via the I2C interface (Register 5, DVS_CFG). The
DVS_CFG register enables DVS and sets the step interval
during the transition (see Table 29).
It is recommended that the user enable the DVS function
before setting the output voltage for Channel 1 or Channel 4.
(The output voltage for Channel 1 is set using the VID1 bits in
Register 2; the output voltage for Channel 4 is set using the
VID4 bits in Register 4.) Enabling DVS after setting the VID
value rapidly changes the output voltage to the next target voltage,
which can result in problems such as a PWRGD failure, an
overvoltage protection (OVP) event, or an overcurrent protection
(OCP) event. Figure 36 shows the dynamic voltage scaling
function.
DVSx_INTVAL SETTING
OUTPUT
25mV FOR CHANNEL 1
(100mV FOR CHANNEL 4)
The internal VREG and VDD regulators are active as long as
PVIN1 is available.
The internal VREG regulator can provide a total load of 95 mA
including the MOSFET driving current, and it can be used as
an always alive 5.1 V power supply for a small system current
demand. The current-limit circuit is included in the VREG
regulator to protect the circuit when the device is heavily loaded.
The VDD regulator is strictly for internal circuit use and is not
recommended for other purposes.
SEPARATE SUPPLY APPLICATIONS
The ADP5051 supports separate input voltages for the four buck
regulators. This means that the input voltages for the four buck
regulators can be connected to different supply voltages.
The PVIN1 voltage provides the power supply for the internal
regulators and the control circuitry. Therefore, if the user plans
to use separate supply voltages for the buck regulators, the PVIN1
voltage must be above the UVLO threshold before the other
channels begin to operate.
To ensure that PVIN1 is high enough to support the outputs in
regulation, use precision enabling to monitor the PVIN1 voltage
and to delay the startup of the outputs. For more information,
see the Precision Enabling section.
The ADP5051 supports cascading supply operation for the four
buck regulators. As shown in Figure 37, PVIN2, PVIN3, and
PVIN4 are powered from the Channel 1 output (VOUT1). In this
configuration, the Channel 1 output voltage must be higher than
the UVLO threshold for PVIN2, PVIN3, and PVIN4.
VIN
PVIN1
PVIN2
TO
PVIN4
BUCK 1
BUCK 2
VOUT1
VOUT2 TO VOUT4
VID FOR
CHANNEL 1 OR
CHANNEL 4
NEW VID CODE
OLD VID CODE
VIDx OLD VID NEW VID
Figure 36. Dynamic Voltage Scaling
During the DVS transition period, the regulator is forced into
PWM operation, and OVP latch-off, SCP latch-off, and hiccup
protection are masked.
INTERNAL REGULATORS (VREG AND VDD)
The internal VREG regulator in the ADP5051 provides a stable
5.1 V power supply for the bias voltage of the MOSFET drivers.
The internal VDD regulator in the ADP5051 provides a stable
3.3 V power supply for internal control circuits. Connect a 1.0 µF
ceramic capacitor between VREG and ground, and connect
another 1.0 µF ceramic capacitor between VDD and ground.
Figure 37. Cascading Supply Application
LOW-SIDE DEVICE SELECTION
The buck regulators in Channel 1 and Channel 2 integrate 4 A
high-side power MOSFET and low-side MOSFET drivers. The
N-channel MOSFETs selected for use with the ADP5051 must be
compatible with the synchronized buck regulators. In general, a
low RDSON N-channel MOSFET achieves higher efficiency; dual
MOSFETs in one package (for both Channel 1 and Channel 2)
are recommended to save space on the printed circuit board
(PCB). For more information, see the Low-Side Power Device
Selection section.
BOOTSTRAP CIRCUITRY
Each buck regulator in the ADP5051 has an integrated bootstrap
regulator. The bootstrap regulator requires a 0.1 µF ceramic
capacitor (X5R or X7R) between the BSTx and SWx pins to
provide the gate drive voltage for the high-side MOSFET.
Rev. B | Page 20 of 55
|
|
Share Link: 