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FDC1004DSCR View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
FDC1004DSCR 4-Channel Capacitance-to-Digital Converter for Capacitive Sensing Solutions TI
Texas Instruments TI
FDC1004DSCR Datasheet PDF : 33 Pages
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www.ti.com
FDC1004
SNOSCY5B – AUGUST 2014 – REVISED APRIL 2015
7.7 I2C Interface Timing
Over recommended operating free-air temperature range, VDD = 3.3 V, for TA = TJ = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
fSCL
tLOW
tHIGH
Clock frequency(1)
Clock low time(1)
Clock high time(1)
10
400
1.3
0.6
tHD;STA
Hold time (repeated) START
After this period, the first clock pulse
0.6
condition (1)
is generated
tSU;STA
tHD;DAT
tSU;DAT
tf
tSU;STO
tBUF
tVD;DAT
tVD;ACK
tSP
Set-up time for a repeated START
condition (1)
Data hold time(1)(2)
Data setup time(1)
SDA fall time(1)
Set-up time for STOP condition(1)
Bus free time between a STOP and
START condition(1)
Data valid time(1)
Data valid acknowledge time(1)
Pulse width of spikes that must be
suppressed by the input filter(1)
IL 3mA; CL 400pF
0.6
0
100
300
0.6
1.3
0.9
0.9
50
UNIT
kHz
µs
µs
µs
µs
ns
ns
ns
µs
µs
ns
ns
ns
(1) This parameter is specified by design and/or characterization and is not tested in production.
(2) The FDC1004 provides an internal 300 ns minimum hold time to bridge the undefined region of the falling edge of SCL.
SDA
tf
SCL
tLOW
tr
START
tHD;STA
tHD;DAT
tHD;STA
tBUF
tr
tf
tSP
tHIGH
tSU;DAT
tSU;STA
REPEATED
START
Figure 1. I2C Timing
tSU;STO
STOP START
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