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ADS8331 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
ADS8331 2.7V~5.5V, 16 Bit 500KSPS Low Power Serial ADC / Low-Power, 16-Bit, 500kSPS, 4-/8-Channel Unipolar Input TI
Texas Instruments TI
ADS8331 Datasheet PDF : 39 Pages
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ADS8331
ADS8332
www.ti.com
SBAS363 – DECEMBER 2009
TIMING CHARACTERISTICS: VA = 2.7V
At TA = –40°C to +85°C, VA = 2.7V, and VBD = 1.65V, unless otherwise noted. (1) (2)
PARAMETER
MIN TYP
MAX
fCCLK Frequency, conversion clock, CCLK
External, fCCLK = 1/2 fSCLK
Internal
0.5
10.5 11
10.5
12.2
tSU1 Setup time, rising edge of CS to EOC
tH1 Hold time, rising edge of CS to EOC
tWL1 Pulse duration, CONVST low
tWH1 Pulse duration, CS high
tSU2 Setup time, rising edge of CS to EOS
tH2 Hold time, rising edge of CS to EOS
tSU3 Setup time, falling edge of CS to first falling edge of SCLK
tWL2 Pulse duration, SCLK low
tWH2 Pulse duration, SCLK high
I/O clock only
1
25
40
40
25
25
14
17
tSCLK – 17
12
tSCLK – 12
40
tSCLK Cycle time, SCLK
I/O and conversion clocks
47.6
I/O clock, daisy-chain mode
40
1000
I/O and conversion clocks,
daisy-chain mode
47.6
1000
tD1 Delay time, falling edge of SCLK to SDO invalid
tD2 Delay time, falling edge of SCLK to SDO valid
tD3 Delay time, falling edge of CS to SDO valid, SDO MSB output
tSU4 Setup time, SDI to falling edge of SCLK
tH3 Hold time, SDI to falling edge of SCLK
tD4 Delay time, rising edge of CS to SDO 3-state
tSU5 Setup time, last falling edge of SCLK before rising edge of CS
tD5 Delay time, falling edge of CS to deactivation of INT
tD6 Delay time, CDI to SDO in daisy-chain mode
10pF load
10pF load
10pF load
10pF load
8
35
35
8
8
10
10
40
35
(1) All input signals are specified with tr = tf = 1.5ns (10% to 90% of VBD) and timed from a voltage level of (VIL + VIH)/2.
(2) See the Timing Diagrams section.
UNIT
MHz
MHz
CCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Copyright © 2009, Texas Instruments Incorporated
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