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ADS8331 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
ADS8331 2.7V~5.5V, 16 Bit 500KSPS Low Power Serial ADC / Low-Power, 16-Bit, 500kSPS, 4-/8-Channel Unipolar Input TI
Texas Instruments TI
ADS8331 Datasheet PDF : 39 Pages
First Prev 31 32 33 34 35 36 37 38 39
ADS8331
ADS8332
SBAS363 – DECEMBER 2009
APPLICATION INFORMATION
TYPICAL CONFIGURATION EXAMPLE
Figure 51 illustrates a typical circuit configuration using the ADS8331/32.
Analog +5V
4.7mF
www.ti.com
22mF
AGND
External
Reference
Input
Host
Processor
AGND
VA REF+ REF- AGND MUXOUT ADCIN INX COM
FS/CS
SDO
SDI
SCLK
CONVST
ADS8331/32
DGND
VBD
Analog Input
Interface
Supply
+1.8V
4.7mF
EOC/INT
Figure 51. Typical Circuit Configuration
POWER-ON SEQUENCE TIMING
During power-on of the ADS8331/32, the digital interface supply voltage (VBD) should not exceed the analog
supply voltage (VA). This condition is specified in the Power-Supply Requirements section of the Electrical
Characteristics tables. If the analog and digital interface supplies for the converter are not generated by a single
voltage source, it is recommended to power-on the analog supply and wait for it to reach its final value before the
digital interface supply is activated. Furthermore, the voltages applied to the analog input pins (INX, ADCIN) and
digital input pins (RESET, FS/CS, SCLK, SDI, and CONVST) should not exceed the voltages on VA and VBD,
respectively, during the power-on sequence. This requirement prevents these input pins from powering the
ADS8331/32 through the ESD protection diodes/circuitry and causing a latch-up condition (see the Electrical
Characteristic tables and Figure 34 for further details).
Communication with the ADS8331/32, such as initiating a conversion with CONVST or writing to the
Configuration register, should not occur for a minimum of 2μs after the analog and digital interface supplies have
finished the power-on sequence and reached the respective final values in the system. This time is required for
the internal POR to activate and place the digital core of the device into the default mode of operation. This
minimum delay time must also be adhered to whenever a reset condition occurs (see the Reset Function section
for additional information).
34
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