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ADS8331 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
ADS8331 2.7V~5.5V, 16 Bit 500KSPS Low Power Serial ADC / Low-Power, 16-Bit, 500kSPS, 4-/8-Channel Unipolar Input TI
Texas Instruments TI
ADS8331 Datasheet PDF : 39 Pages
First Prev 31 32 33 34 35 36 37 38 39
ADS8331
ADS8332
SBAS363 – DECEMBER 2009
www.ti.com
Figure 49 shows a slightly different scenario where CONVST is not shared with the second converter. Converters
#1 and #3 have the same CONVST signal. In this case, converter #2 simply passes previous conversion data
downstream.
Manual Trigger, Read While Sampling
(Use internal CCLK, EOC active low, and TAG mode disabled)
CONVST #1
CONVST #3
CONVST #2
EOC #1
(active low)
CS #1
SCLK #1
SCLK #2
SCLK #3
SDO #1
CDI #2
CS #2
CS #3
Conversion N
tCONV = 18 CCLK
High-Z
1. . . . . . . . . . . . . .16
Conversion N
from Device #1
tSAMPLE1 = 3 CCLK min
1. . . . . . . . . . . . . .16
1. . . . . . . . . . . . . .16
tSU2
High-Z
tSU2
SDO #2
CDI #3
High-Z
Conversion (N - 1)
from Device #2(1)
Conversion N
from Device #1
High-Z
SDO #3
High-Z
Conversion N
from Device #3
Conversion (N - 1)
from Device #2(1)
Conversion N
from Device #1
High-Z
SDI #1
SDI #2
SDI #3
Don't Care
Configure
Read Data
Read Data
Don't Care
(1) Data from device #2 is from previous converison.
Figure 49. Simplified Daisy-Chain Mode Timing with Separate CONVST and Continuous CS
The number of SCLKs required for a serial read cycle depends on the combination of different read modes, TAG
mode, daisy-chain mode, and the manner in which a channel is selected (for example, Auto Channel Select
mode). The required number of SCLKs for different readout modes are listed in Table 7.
Table 7. Required SCLKs For Different Readout Mode Combinations
DAISY-CHAIN MODE
CFR_D5
1
1
0
0
TAG MODE
CFR_D1
0
1
0
1
NUMBER OF SCLK CYCLES
PER SPI READ
16
19
16
24
TRAILING BITS
None
TAG bits plus up to 5 zeros
None
TAG bits plus 5 zeros
32
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