SBAS363 – DECEMBER 2009
Start of a Conversion
The end of acquisition is the same as the start of a conversion. This process is initiated by bringing the CONVST
pin low for a minimum of 40ns. After the minimum requirement has been met, the CONVST pin can be brought
high. CONVST acts independently of FS/CS so it is possible to use one common CONVST for applications that
require simultaneous sample/hold with multiple converters. The ADS8331/32 switches from sample to hold mode
on the falling edge of the CONVST signal. The ADS8331/32 requires 18 conversion clock (CCLK) cycles to
complete a conversion. The conversion time is equivalent to 1500ns with a 12MHz internal clock. The minimum
time between two consecutive CONVST signals is 21 CCLKs.
A conversion can also be initiated without using CONVST if the ADS8331/32 is programmed for Auto-Trigger
mode (CFR_D9 = '0'). When the converter is configured in this mode, and with CFR_D8 = '0', the next
conversion is automatically started three conversion clocks (CCLK) after the end of a conversion. These three
conversion clocks (CCLK) are used for the acquisition time. In this case, the time to complete one acquisition
and conversion cycle is 21 CCLKs. Table 1 summarizes the different conversion modes.
Table 1. Different Types of Conversion
Auto Channel Select(1)
No need to write channel number to CMR. Use internal sequencer for
Manual Channel Select
Write channel number to CMR
Start a conversion based on conversion
Start a conversion with CONVST
(1) Auto channel select should be used with Auto-Trigger mode and TAG bit output enabled.
Status Output Pin (EOC/INT)
The status output pin is programmable. It can be used as an EOC output (CFR_D[7:6] = '11') where the low time
is equal to the conversion time. When the status pin is programmed as EOC and the polarity is set as active low,
the pin works in the following manner: the EOC output goes low immediately following CONVST going low with
Manual-Trigger mode enabled. EOC stays low throughout the conversion process and returns high when the
conversion has ended. If Auto-Trigger mode is enabled, the EOC output remains high for three conversion clocks
(CCLK) after the previous rising edge of EOC .
This status pin can also be used as an interrupt output, INT (CFR_D[7:6] = '10'), which is set low at the end of a
conversion, and is brought high (cleared) by the next read cycle. The polarity of this pin, whether used as EOC
or INT, is programmable through the CFR_D7 bit.
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