Electronic component search and free download site.
Transistors,MosFET ,Diode,Integrated circuits

TMP007AIYZFT データシートの表示(PDF) - Texas Instruments

部品番号コンポーネント説明メーカー
TMP007AIYZFT Infrared Thermopile Sensor with Integrated Math Engine TI
Texas Instruments TI
TMP007AIYZFT Datasheet PDF : 55 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
TMP007
SBOS685C – APRIL 2014 – REVISED JULY 2015
www.ti.com
7.3.8.9 Two-Wire Timing
The TMP007 is two-wire and SMBus compatible. Figure 23 to Figure 26 describe the various operations on the
TMP007. Parameters for Figure 23 are defined in Table 5. Bus definitions are:
Bus Idle Both SDA and SCL lines remain high.
Start Data Transfer A change in the state of the SDA line, from high to low, while the SCL line is high defines a
start condition. Each data transfer is initiated with a start condition.
Stop Data Transfer A change in the state of the SDA line from low to high while the SCL line is high defines a
stop condition. Each data transfer is terminated with a repeated start or stop condition.
Data Transfer The number of data bytes transferred between a start and a stop condition is not limited, and is
determined by the master device.
The receiver acknowledges the transfer of data. It is also possible to use the TMP75B for
single-byte updates. To update only the MS byte, terminate communication by issuing a start
or stop condition on the bus.
Acknowledge Each receiving device, when addressed, must generate an acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock
pulse so that the SDA line is stable low during the high period of the acknowledge clock
pulse. Setup and hold times must be taken into account. When a master receives data, the
termination of the data transfer can be signaled by the master generating a not-acknowledge
(1) on the last byte transmitted by the slave.
f(SCL)
t(BUF)
t(HDSTA)
t(SUSTA)
t(SUSTO)
t(HDDAT)
t(SUDAT)
t(LOW)
t(HIGH)
tF, tR – SDA
tF, tR – SCL
tR
Table 5. Two-Wire Timing Requirements
SCL operating frequency
Bus free time between stop and start condition
Hold time after repeated start condition.
After this period, the first clock is generated.
Repeated start condition setup time
Stop condition setup time
Data hold time
Data setup time
SCL clock low period
SCL clock high period
Data fall and rise time
Clock fall and rise time
Rise time for SCL 100 kHz
FAST MODE
MIN
MAX
0.001
0.4
1300
600
HIGH-SPEED MODE
MIN
MAX
0.001
2.5
260
160
600
160
600
160
0
900
0
150
100
30
1300
260
600
60
300
80
300
40
1000
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
Submit Documentation Feedback
Product Folder Links: TMP007
Copyright © 2014–2015, Texas Instruments Incorporated
Direct download click here

 

Share Link : 
All Rights Reserved© datasheetq.com 2015 - 2019  ] [ Privacy Policy ] [ Request Datasheet  ] [ Contact Us ]