AVCC = DVCC = 4.75 V to 5.25 V; VDD = 5 V to 16.5 V; VSS = −16.5 V to −5 V; VDRIVE = 2.7 V to 5.25 V; TA = TMIN to TMAX, unless otherwise noted.1
2.7 V ≤ VDRIVE ≤ 5.25 V
0.3 × tSCLK
0.3 × tSCLK
Conversion time, internal clock. CONVST falling edge to BUSY falling edge.
For the AD7367-5.
For the AD7366-5.
Frequency of serial read clock.
Minimum quiet time required between the end of serial read and the start of the next
Minimum CONVST low pulse.
CONVST falling edge to BUSY rising edge.
BUSY falling edge to MSB valid once CS is low for t4 prior to BUSY going low.
Delay from CS falling edge until Pin 1 (DOUTA) and Pin 23 (DOUTB) are three-state disabled.
Data access time after SCLK falling edge.
SCLK to data valid hold time.
SCLK low pulse width.
SCLK high pulse width.
CS rising edge to DOUTA, DOUTB, high impedance.
Power up time from shutdown mode; time required between CONVST rising edge and
CONVST falling edge.
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the
Terminology section and Figure 25.
2 The time required for the output to cross is 0.4 V or 2.4 V.
Rev. B | Page 7 of 28