|Description||True Bipolar Input, 12-/14-Bit, 2-Channel, Simultaneous Sampling SAR ADCs|
|AD7366BRUZ-5 Datasheet PDF : 29 Pages |
Figure 25 and Figure 26 show the detailed timing diagram for
serial interfacing to the AD7366-5 and the AD7367-5. On the
falling edge of CNVST, the AD7366-5/AD7367-5 simultaneously
convert the selected channels. These conversions are performed
using the on-chip oscillator. After the falling edge of CNVST,
the BUSY signal goes high, indicating that the conversion has
started. The BUSY signal returns low when the conversion has
been completed. The data can now be read from the DOUT pins.
The CS and SCLK signals are required to transfer data from the
AD7366-5/AD7367-5. The AD7366-5/AD7367-5 have two
output pins corresponding to each ADC. Data can be read from
the AD7366-5/ AD7367-5 using both DOUTA and DOUTB.
Alternatively, a single output pin of the user’s choice can be used.
The SCLK input signal provides the clock source for the serial
interface. The CS goes low to access data from the AD7366-
5/AD7367-5. The falling edge of CS takes the bus out of three-
state and clocks out the MSB of the conversion result. The data
stream consists of 12 bits of data for the AD7366-5 and 14 bits of
data for the AD7367-5, MSB first. The first bit of the conversion
result is valid on the first SCLK falling edge after the CS falling
edge. The subsequent 11-bits/ 13-bits of data for the AD7366-
5/AD7367-5, respectively, are clocked out on the falling edge of
the SCLK signal. A minimum of 12 clock pulses must be
provided to the AD7366-5 to access each conversion result, and
a minimum of 14 clock pulses must be provided to the AD7367-
5 to access the conversion result. Figure 25 shows how a 12
SCLK read is used to access the conversion results for the
AD7366-5, and Figure 26 illustrates the case for the AD7367-5
with a 14 SCLK read.
On the rising edge of CS, the conversion is terminated, and
DOUTA and DOUTB return to three-state. If CS is not brought high
but is instead held low for an additional 14 SCLK cycles, the
data from the other DOUT pin follows on the selected DOUT pin.
Note that the second serial result from the AD7366-5 is
preceded by two zeros. See Figure 27 and Figure 28, where
DOUTA is shown. In this case, the DOUT line in use returns to
three-state on the rising edge of CS.
If the falling edge of SCLK coincides with the falling edge of CS,
the falling edge of SCLK is not acknowledged by the AD7366-5/
AD7367-5, and the next falling edge of SCLK is the first registered
after the falling edges of the CS.
The CS pin can be brought low before the BUSY signal goes low,
indicating the end of a conversion. When CS is at a logic low state,
the data bus is brought out of three-state. This feature can be
used to ensure that the MSB is valid on the falling edge of BUSY
by bringing CS low a minimum of t4 before the BUSY signal
goes low. The dotted CS line in Figure 22 and Figure 23
illustrates this feature.
Alternatively, the CS pin can be tied to a low logic state continu-
ously. In this case, the DOUT pins never enter three-state, and the
data bus is continuously active. Under these conditions, the MSB
of the conversion result for the AD7366-5/AD7367-5 is available
on the falling edge of the BUSY signal. The next most significant
bit is available on the first SCLK falling edge after the BUSY
signal has gone low. This mode of operation enables the user to
read the MSB as soon as it is made available by the converter.
Figure 25. Serial Interface Timing Diagram for the AD7366-5
Figure 26. Serial Interface Timing Diagram for the AD7367-5
Rev. B | Page 22 of 28
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