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AD7366BRUZ-5 View Datasheet(PDF) - Analog Devices

Part NameAD7366BRUZ-5 ADI
Analog Devices ADI
DescriptionTrue Bipolar Input, 12-/14-Bit, 2-Channel, Simultaneous Sampling SAR ADCs
AD7366BRUZ-5 Datasheet PDF : 29 Pages
First Prev 21 22 23 24 25 26 27 28 29
AD7366-5/AD7367-5
MODES OF OPERATION
The mode of operation for the AD7366-5/AD7367-5 is selected
by the (logic) state of the CNVST signal at the end of a conver-
sion. There are two possible modes of operation: normal mode
and shutdown mode. These modes of operation are designed to
provide flexible power management options, which can be
chosen to optimize the power dissipation/throughput rate
ratio for differing application requirements.
NORMAL MODE
Normal mode is intended for applications needing fast
throughput rates because the user does not have to worry
about any power-up times (with the AD7366-5/AD7367-5
remaining fully powered at all times). Figure 22 shows the
normal mode of operation for the AD7366-5, while Figure 23
illustrates normal mode for the AD7367-5.
The conversion is initiated on the falling edge of CNVST as
described in the Circuit Information section. To ensure that
the part remains fully powered up at all times, CNVST must be
at a logic high state prior to the BUSY signal going low. If
CNVST is at a logic low state when the BUSY signal goes low,
the analog circuitry powers down and the part ceases converting.
The BUSY signal remains high for the duration of the conversion.
The CS pin must be brought low to bring the data bus out of
three-state; subsequently 12 SCLK cycles are required to read
the conversion result from the AD7366-5, while 14 SCLK cycles
are required to read from the AD7367-5. The DOUT lines return
to three-state only when CS is brought high. If CS is left low for
a further 12 SCLK cycles for the AD7366-5 or 14 SCLK cycles
for the AD7367-5, the result from the other on-chip ADC is
also accessed on the same DOUT line, as shown in Figure 27 and
Figure 28 (see the Serial Interface section).
After 24 SCLK cycles have elapsed for the AD7366-5 and 28 SCLK
cycles have elapsed for the AD7367-5, the DOUT line returns to
three-state when CS is brought high (not on the 24th or 28th SCLK
falling edge). If CS is brought high prior to this, the DOUT line
returns to three-state at that point. Thus, CS must be brought
high once the read is completed because the bus does not
automatically return to three-state upon completion of the
dual result read.
Once a data transfer is complete and DOUTA and DOUTB have
returned to three-state, another conversion can be initiated after
the quiet time, tQUIET, has elapsed by bringing CNVST low again.
CNVST
BUSY
CS
SCLK
t1
t2
tCONVERT
t3
tQUIET
SERIAL READ OPERATION
1
12
Figure 22. Normal Mode Operation for the AD7366-5
CNVST
BUSY
CS
SCLK
t1
t2
tCONVERT
t3
tQUIET
SERIAL READ OPERATION
1
14
Figure 23. Normal Mode Operation for the AD7367-5
Rev. B | Page 20 of 28
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