Each ADC in the AD7366-5/AD7367-5 has two single-ended
analog inputs. Figure 18 shows the equivalent circuit of the
analog input structure of the AD7366-5/AD7367-5. The two
diodes provide ESD protection. Care must be taken to ensure
that the analog input signals never exceed the supply rails by
more than 300 mV. Otherwise, these diodes become forward-
biased and start conducting current into the substrate. The
diodes can conduct up to 10 mA without causing irreversible
damage to the part. The resistors are lumped components made
up of the on resistance of the switches. The value of these resistors
is typically 170 Ω. Capacitor C1 can primarily be attributed to
pin capacitance while Capacitor C2 is the sampling capacitor of
the ADC. The total lumped capacitance of C1 and C2 is approxi-
mately 9 pF for the ±10 V input range and approximately 13 pF
for all other input ranges.
The output coding of the AD7366-5/AD7367-5 is twos comple-
ment. The designed code transitions occur at successive integer
LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size is
dependent on the analog input range selected (see Table 10).
The ideal transfer characteristic is shown in Figure 19.
Table 10. LSB Sizes for Each Analog Input Range
Full-Scale LSB Size Full-Scale
20 V/4096 4.88
20 V/16384 1.22
10 V/4096 2.44
10 V/16384 0.61
0 V to +10 V 10 V/4096 2.44
10 V/16384 0.61
Figure 18. Equivalent Analog Input Structure
The AD7366-5/AD7367-5 can handle true bipolar input voltages.
The analog input can be set to one of three ranges: ±10 V, ±5 V, or
0 V to +10 V. The logic levels on Pin RANGE0 and Pin RANGE1
determine which input range is selected as outlined in Table 8.
These range bits should not be changed during the acquisition
time prior to a conversion, but can change at any other time.
Table 8. Analog Input Range Selection
0 V to +10 V
Do not program
The parts require VDD and VSS dual supplies for the high voltage
analog input structures. These supplies must be greater than or
equal to ±5 V (see Table 7 for the requirements on these supplies).
The AD7366-5/AD7367-5 require a low voltage 4.75 V to 5.25 V
AVCC supply to power the ADC core, a 4.75 V to 5.25 V DVCC
supply for digital power, and a 2.7 V to 5.25 V VDRIVE supply for
–FSR/2 + 1LSB
+FSR/2 – 1LSB
Figure 19. Transfer Characteristic
The track-and-hold on the analog input of the AD7366-5/
AD7367-5 allows the ADC to accurately convert an input sine
wave of full-scale amplitude to 12-/14-bit accuracy. The input
bandwidth of the track-and-hold is greater than the Nyquist
rate of the ADC. The AD7366-5/AD7367-5 can handle
frequencies up to 35 MHz.
The track-and-hold enters its tracking mode once the BUSY
signal goes low after the CS falling edge. The time required to
acquire an input signal depends on how quickly the sampling
capacitor is charged. With zero source impedance, 140 ns is
sufficient to acquire the signal to the 12-bit level for the AD7366-5
and the 14-bit level for the AD7367-5. The acquisition time for
the ±10 V, ±5 V, and 0 V to +10 V ranges to settle to within ±½ LSB
is typically 140 ns. The ADC goes back into hold mode on the
falling edge of CNVST.
Channel selection is made via the ADDR pin as shown in Table 9.
The logic level on the ADDR pin is latched on the rising edge of
the BUSY signal for the next conversion, not the one in progress.
When power is first supplied to the AD7366-5/AD7367-5, the
The acquisition time required is calculated using the following
tACQ = 10 × ((RSOURCE + R) × C)
default channel selection is VA1 and VB1.
Table 9. Channel Selection
C is the sampling capacitance.
R is the resistance seen by the track-and-hold amplifier looking
at the input.
RSOURCE should include any extra source impedance on the
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