Pin No. Mnemonic
Internal/External Reference Selection, Logic Input. If this pin is tied to logic high, the on-chip 2.5 V reference is
used as the reference source for both ADC A and ADC B. In addition, Pin DCAPA and Pin DCAPB must be tied to
decoupling capacitors. If the REFSEL pin is tied to GND, an external reference can be supplied to the AD7366-5/
AD7367-5 through the DCAPA and/or DCAPB pins.
Chip Select, Active Low Logic Input. This input frames the serial data transfer. When CS is logic low, the output bus
is enabled, and the conversion result is output on DOUTA and DOUTB.
Serial Clock, Logic Input. A serial clock input provides the SCLK for accessing the data from the AD7366-5/AD7367-5.
Conversion Start, Logic Input. This pin is edge triggered. On the falling edge of this input, the track/hold goes into
hold mode and the conversion is initiated. If CNVST is low at the end of a conversion, the part goes into power-
down mode. In this case, the rising edge of CNVST instructs the part to power up again.
Busy Output. BUSY transitions high when a conversion starts and remains high until the conversion completes.
Digital Ground. This is the ground reference point for all digital circuitry on the AD7366-5/AD7367-5. The DGND
pin should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same
potential and must not be more than 0.3 V apart, even on a transient basis.
Rev. B | Page 10 of 28