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AD8319ACPZ-R7-2005 View Datasheet(PDF) - Analog Devices

Part NameAD8319ACPZ-R7(2005) ADI
Analog Devices ADI
Description1 MHz to 10 GHz, 45 dB Log Detector/Controller
AD8319ACPZ-R7 Datasheet PDF : 20 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
Table 5. Evaluation Board (Rev. A) Configuration Options
R1, C1, C2
Supply and Ground Connections.
Input Interface.
The 52.3 Ω resistor in position R1 combines with the AD8319's internal input impedance to give a
broadband input impedance of about 50 Ω. Capacitor C1 and Capacitor C2 are dc-blocking capacitors. A
reactive impedance match can be implemented by replacing R1 with an inductor and C1 and C2 with
appropriately valued capacitors.
R5, R7
R2, R3, R4, R6,
Temperature Compensation Interface.
The internal temperature compensation network is optimized for input signals up to 3.6 GHz when R7 is 10
kΩ. This circuit can be adjusted to optimize performance for other input frequencies by changing the
value of the resistor in position R7. See Table 4 for specific TADJ resistor values.
Output Interface—Measurement Mode.
In measurement mode, a portion of the output voltage is fed back to Pin VSET via R2. The magnitude of the
slope of the VOUT output voltage response
can be increased by reducing the portion of VOUT that is fed back to VSET.
R6 can be used as a back-terminating resistor or as part of a single-pole low-pass filter.
R2, R3
C4, C5,
Output Interface—Controller Mode.
In this mode, R2 must be open. In controller mode, the AD8319 can control the gain of an external
component. A setpoint voltage is applied to Pin VSET, the value of which corresponds to the desired RF
input signal level applied to the AD8319 RF input. A sample of the RF output signal from this variable-gain
component is selected, typically via a directional coupler, and applied to AD8319 RF input. The voltage
at Pin VOUT is applied to the gain control of the variable gain element. A control voltage is applied to Pin
VSET. The magnitude of the control voltage can optionally be attenuated via the voltage divider comprising
R2 and R3, or a capacitor can be installed in position R3 to form a low-pass filter along with R2.
Power Supply Decoupling.
The nominal supply decoupling consists of a 100 pF filter capacitor placed physically close to the
AD8319 and a 0.1 μF capacitor placed nearer to the power supply input pin.
Filter Capacitor.
The low-pass corner frequency of the circuit that drives Pin VOUT can be lowered by placing a capacitor
between CLPF and ground. Increasing this capacitor increases the overall rise/fall time of the AD8319 for
pulsed input signals. See the Output Filtering section for more details.
Not applicable
R1 = 52.3 Ω
(Size 0402)
C1 = 47 nF
(Size 0402)
C2 = 47 nF
(Size 0402)
R5 = 200 Ω
(Size 0402)
R7 = open
(Size 0402)
R2 = 0 Ω (Size
R3 = open
(Size 0402)
R4 = open
(Size 0402)
R6 = 1 kΩ (Size
RL = CL =
open (Size
R2 = open
(Size 0402)
R3 = open
(Size 0402)
C5 = 100 pF
(Size 0402)
C4 = 0.1 μF
(Size 0603)
C3 = 8.2 pF
(Size 0402)
Rev. 0 | Page 16 of 20
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