|Description||1 MHz to 10 GHz, 45 dB Log Detector/Controller|
|AD8319ACPZ-R7 Datasheet PDF : 20 Pages |
Although demodulating log amps respond to input signal
voltage, not input signal power, it is customary to discuss the
amplitude of high frequency signals in terms of power. In this
case, the characteristic impedance of the system, Z0, must be
known to convert voltages to their corresponding power levels.
The following equations are used to perform this conversion.
P(dBm) = 10 × log10(Vrms2/(Z0 × 1 mW))
P(dBV) = 20 × log10(Vrms/1 Vrms)
P(dBm) = P(dBV) − 10 × log10(Z0 × 1 mW/1 Vrms2)
For example, PINTERCEPT for a sinusoidal input signal expressed in
terms of dBm (decibels referred to 1 mW), in a 50 Ω system is
PINTERCEPT(dBm) = PINTERCEPT(dBV) − 10 × log10(Z0 ×
1 mW/1 Vrms2) =
+2 dBV − 10 × log10(50×10-3) = +15 dBm
For a square wave input signal in a 200 Ω system
PINTERCEPT = −1 dBV − 10 × log10[(200 Ω × 1 mW/1Vrms2)]
= +6 dBm
Further information on the intercept variation dependence upon
waveform can be found in the AD8313 and AD8307 data sheets.
SETTING THE OUTPUT SLOPE
IN MEASUREMENT MODE
To operate in measurement mode, VOUT must be connected
to VSET. Connecting VOUT directly to VSET yields the nominal
logarithmic slope of −22 mV/dB. The output swing corresponding
to the specified input range is then 0.35 V to 1.5 V. The slope
and output swing can be increased by placing a resistor divider
between VOUT and VSET (that is, one resistor from VOUT to
VSET and one resistor from VSET to ground). The input imped-
ance of VSET is 40 kΩ. Slope-setting resistors should be kept below
20 kΩ to prevent this input impedance from affecting the
resulting slope. If two equal resistors are used (for example,
10 kΩ/10 kΩ), the slope doubles to −44 mV/dB.
Figure 28. Increasing the Slope
The AD8319 provides a controller mode feature at the VOUT
pin. Using VSET for the setpoint voltage, it is possible for the
AD8319 to control subsystems, such as power amplifiers (PAs),
variable gain amplifiers (VGAs), or variable voltage attenuators
(VVAs) that have output power that increases monotonically
with respect to their gain control signal.
To operate in controller mode, the link between VSET and
VOUT is broken. A setpoint voltage is applied to the VSET
input; VOUT is connected to the gain control terminal of the
variable gain amplifier (VGA) and the detector’s RF input is
connected to the output of the VGA (usually using a directional
coupler and some additional attenuation). Based on the defined
relationship between VOUT and the RF input signal when the
device is in measurement mode, the AD8319 adjusts the voltage
on VOUT (VOUT is now an error amplifier output) until the
level at the RF input corresponds to the applied VSET. When the
AD8319 operates in controller mode, there is no defined relation-
ship between VSET and VOUT voltage; VOUT settles to a value that
results in the correct input signal level appearing at INHI/INLO.
For this output power control loop to be stable, a ground-
referenced capacitor must be connected to the CLPF pin. This
capacitor, CFLT, integrates the error signal (in the form of a
current) to set the loop bandwidth and ensure loop stability.
Further details on control loop dynamics can be found in the
AD8315 data sheet.
Figure 29. AD8319 Controller Mode
Decreasing VSET, which corresponds to demanding a higher
signal from the VGA, increases VOUT. The gain control voltage
of the VGA must have a positive sense. A positive control
voltage to the VGA increases the gain of the device.
Rev. 0 | Page 13 of 20
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