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AD8319ACPZ-R7-2005 View Datasheet(PDF) - Analog Devices

Part NameAD8319ACPZ-R7(2005) ADI
Analog Devices ADI
Description1 MHz to 10 GHz, 45 dB Log Detector/Controller
AD8319ACPZ-R7 Datasheet PDF : 20 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
AD8319
USING THE AD8319
BASIC CONNECTIONS
The AD8319 is specified for operation up to 10 GHz, as a result,
low impedance supply pins with adequate isolation between
functions are essential. A power supply voltage of between 3.0 V
and 5.5 V should be applied to VPOS. Power supply decoupling
capacitors of 100 pF and 0.1 μF should be connected close to
this power supply pin.
VS(2.7V–5.5V)
C5
0.1μF R2
C4 0Ω
100pF
C2
SEE TEXT
SIGNAL
INPUT
R1
52.3Ω
47nF
C1
47nF
8
INLO
INHI
1
7
6
VPOS TADJ
AD8319
COMM CLPF
2
3
5
VOUT
VSET
4
SEE TEXT
Figure 22. Basic Connections
VOUT
R4
0Ω
The paddle of the LFCSP package is internally connected to
COMM. For optimum thermal and electrical performance, the
paddle should be soldered to a low impedance ground plane.
INPUT SIGNAL COUPLING
The RF input (INHI) is single-ended and must be ac-coupled.
INLO (input common) should be ac-coupled to ground.
Suggested coupling capacitors are 47 nF ceramic 0402-style
capacitors for input frequencies of 1 MHz to 10 GHz. The
coupling capacitors should be mounted close to the INHI and
INLO pins. The coupling capacitor values can be increased to
lower the input stage’s high-pass cutoff frequency. The high-
pass corner is set by the input coupling capacitors and the
internal 10 pF high-pass capacitor. The dc voltage on INHI and
INLO is about one diode voltage drop below VPOS.
VPOS
5pF
18.7kΩ
INHI
INLO
CURRENT
5pF
18.7kΩ
2kΩ
FIRST
GAIN
STAGE
A = 9dB
Gm
STAGE
Figure 23. Input Interface
OFFSET
COMP
While the input can be reactively matched, in general this is not
necessary. An external 52.3 Ω shunt resistor (connected on the
signal side of the input coupling capacitors, as shown in Figure 22)
combines with the relatively high input impedance to give an
adequate broadband 50 Ω match.
The coupling time constant, 50 × CC/2, forms a high-pass
corner with a 3 dB attenuation at fHP = 1/(2π × 50 × CC ), where
C1 = C2 = CC. Using the typical value of 47 nF, this high-pass
corner will be ~68 kHz. In high frequency applications, fHP
should be as large as possible to minimize the coupling of
unwanted low frequency signals. In low frequency applications,
a simple RC network forming a low-pass filter should be added
at the input for similar reasons. This should generally be placed
at the generator side of the coupling capacitors, thereby
lowering the required capacitance value for a given high-pass
corner frequency.
OUTPUT INTERFACE
The VOUT pin is driven by a PNP output stage. An internal 10 Ω
resistor is placed in series with the output and the VOUT pin.
The rise time of the output is limited mainly by the slew on
CLPF. The fall time is an RC-limited slew given by the load
capacitance and the pull-down resistance at VOUT. There is an
internal pull-down resistor of 1.6 kΩ. A resistive load at VOUT
is placed in parallel with the internal pull-down resistor to
provide additional discharge current.
VPOS
CLPF
+
0.8V
10Ω
VOUT
1200Ω
COMM
400Ω
Figure 24. Output Interface
To reduce the fall time, VOUT should be loaded with a resistive
load of <1.6 kΩ. For example, with an external load of 150 Ω
the AD8319 fall time is <7 ns.
SETPOINT INTERFACE
The VSET input drives the high impedance (20 kΩ) input of an
internal op amp. The VSET voltage appears across the internal
1.5 kΩ resistor to generate ISET. When a portion of VOUT is
applied to VSET, the feedback loop forces
−ID × log10(VIN/VINTERCEPT) = ISET.
If VSET = VOUT/2x, then ISET = VOUT/(2x × 1.5 kΩ).
The result is
VOUT = (−ID × 1.5 kΩ × 2x) × log10(VIN/VINTERCEPT)
Rev. 0 | Page 11 of 20
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