NXP Semiconductors
8.7 AHB multilayer matrix
LPC15xx
32-bit ARM Cortex-M3 microcontroller
TEST/DEBUG
INTERFACE
ARM
CORTEX-M3
System I-code D-code
bus
bus
bus
USB
DMA masters
AHB-TO-APB
BRIDGE0
slaves
FLASH
SRAM0
SRAM1
SRAM2
ROM
EEPROM
HS GPIO
SCTIMER0/PWM
SCTIMER1/PWM
SCTIMER2/PWM
SCTIMER3/PWM
CRC
ADC0
DAC
ACMP INPUT MUX RTC
WWDT SWM
PMU USART1 USART2 SPI0
AHB MULTILAYER MATRIX
AHB-TO-APB
BRIDGE1
SPI1 I2C0 QEI SYSCON
ADC1
MRT
PINT
GINT0
GINT1
= master-slave connection
Fig 9. AHB multilayer matrix
LPC15XX
Product data sheet
RIT SCTIPU FLASH CTRL USART2 C_CAN
IOCON EEPROM CTRL
aaa-010870
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 29 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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