SMJ27C512-15JM View Datasheet(PDF) - Austin Semiconductor
Part Name
Description
Manufacturer
SMJ27C512-15JM Datasheet PDF : 11 Pages
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Austin Semiconductor, Inc.
UVEPROM
SMJ27C512
READ/OUTPUT DISABLE
When the outputs of two or more SMJ27C512 are connected
in parallel on the same bus, the output of any particular device
in the circuit can be read with no interference from
competing outputs of the other devices. To read the output of
the selected SMJ27C512, a low-level signal is applied to the
E\ and G\ /VPP. All other devices in the circuit should have
their outputs disabled by applying a high-level signal to one of
these pins. Output data is accessed at pins DQ0 through DQ7.
LATCHUP IMMUNITY
Latchup immunity on the SMJ27C512 is a minimum of 250mA
on all inputs and outputs. This feature provides latchup
immunity beyond any potential transients at the printed
circuit board level when the EPROM is interfaced to
industry-standard TTL or MOS logic devices. Input/output
layout approach controls latchup without compromising
performance or packing density.
POWER DOWN
Active ICC supply current can be reduced from 35mA to
500µA(TTL-level inputs) or 300µA (CMOS-level inputs) by
applying a high TTL/CMOS signal to the E\ pin. In this mode
all outputs are in the high-impedance state.
SNAP! PULSE PROGRAMMING
The SMJ27C512 is programmed using the SNAP! Pulse
programming algorithm as illustrated by the flowchart in
Figure 1. This algorithm programs in a nominal time of seven
seconds. Actual programming time varies as a function of the
programmer used.
Data is presented in parallel (eight bits) on pins DQ0 to DQ7.
Once addresses and data are stable, E\ is pulsed. The SNAP!
Pulse programming algorithm uses an initial pulse of 100µs
followed by a byte verification to determine when the addressed
byte has been successfully programmed. Up to ten 100µs
pulses per byte are provided before a failure is recognized.
The programming mode is achieved when G\ /VPP = 13V,
VCC= 6.5V, and E\ = VIL. More than one device can be
programmed when the devices are connected in parallel.
Locations can be programmed in any order. When the SNAP!
Pulse programming routine is complete, all bits are verified
with VCC = 5V, G\ /VPP = VIL, and E\ = VIL.
PROGRAM INHIBIT
Programming can be inhibited by maintaining high level
input on E\.
ERASURE
Before programming, the SMJ27512 is erased by exposing
the chip through the transparent lid to a high-intensity ultra-
violet (UV) light (wavelength 2537 Å). EPROM erasure
before programming is necessary to assure that all bits are in
the logic-high state. Logic lows are programmed into the
desired locations. A programmed logic low can be erased
only by ultraviolet light. The recommended minimum
exposure dose (UV intensity x exposure time) is 15 W.s/cm2.
A typical 12mW/cm2, filterless UV lamp erases the device in
21 minutes. The lamp should be located about 2.5cm above
the chip during erasure. After erasure, all bits are in the high
state. It should be noted that normal ambient light contains
the correct wavelength for erasure; therefore, when using
the SMJ27C512, the window should be covered with an opaque
label.
PROGRAM VERIFY
Programmed bits can be verified with G\ /VPP and E\ = VIL.
SIGNATURE MODE
The signature mode provides access to a binary code
identifying the manufacturer and device type. This mode is
activated when A9 (terminal 24) is forced to 12V ±0.5V. Two
identifier bytes are accessed by A0 (terminal 10); i.e.,
A0 = VIL accesses the manufacturer code, which is output on
DQ0-DQ7; A0 = VIH accesses the device code, which is also
output on DQ0-DQ7. All other addresses must be held at VIL.
Each byte possesses odd parity on bit DQ7. The
manufacturer code for these devices is 97h and the device
code is 85h.
SMJ27512
Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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