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M2004-01-690.5692 View Datasheet(PDF) - Integrated Circuit Systems

Part Name
Description
Manufacturer
M2004-01-690.5692
ICST
Integrated Circuit Systems ICST
M2004-01-690.5692 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
Micro Networks
An Integrated Circuit Systems Company
M2004-01
Preliminary Specifications
TABLE 2
Pin Number
1, 2, 3
4, 9
5, 8
6, 7
10, 14, 26
11, 19, 33
12, 13
PIN DESCRIPTIONS
Name
GND
OP_IN, nOP_IN
nOP_OUT, OP_OUT
nVC, VC
GND
VDD
N0, N1
I/O
GND
Analog I/O
Analog I/O
Input
GND
Power
Input
Configuration
VCSO
Pull - down
15, 16
17
FOUT, nFOUT
MR
Output
Input
Unterminated
Pull - down
18
S_CLOCK
Input
Pull - down
20
S_DATA
Input
Pull - down
21
S_LOAD
Input
Pull - down
22
nP_LOAD
Input
Pull - down
23
REF_ CLK 1
Input
24
REF_ CLK 0
Input
25
REF_SEL
Input
27, 28, 29, 30, 31 M0, M1, M2, M3, M4 Input
32
M5
Input
34, 35, 36
DNC
Pull - down
Pull - down
Pull - down
Pull - down
Pull - down
Description
Power Supply Ground
Used for external loop filter. See Figure 2.
Used for external loop filter. See Figure 2
Differential Control Voltage Input Pair
Power Supply Ground
Positive Supply Pins
Determines the output divider value as defined in
table 3C. LVCMOS / LVTTL interface levels.
Differential output, 3.3V LVPECL levels.
Logic HIGH resets the reference frequency and N
output dividers. Logic LOW enables the outputs.
LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input
into the shift register on the rising edge of
S_CLOCK.
Shift register serial input. Data is sampled on the
rising edge of S_CLOCK.
Controls transition of data from shift register into
the dividers. LVCMOS / LVTTL interface levels
Parallel load input. Determines when data
present at M5:M0 is loaded into Mdivider, and
when data present at N1:N0 sets the N output
divider value. LVCMOS / LVTTL interface levels.
Input reference clock. LVCMOS / LVTTL interface
levels.
Input reference clock. LVCMOS / LVTTL interface
levels.
Selects between the different reference clock
inputs as the PLL reference source. See table 3D.
LVCMOS / LVTTL interface levels.
M divider inputs. Data is latched on LOW-to-HIGH
transition of nP_LOAD input. LVCMOS/ LVTTL
interface levels.
Do not connect. Internal test pins must be left
floating.
Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com
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