DatasheetQ Logo
Electronic component search and free download site.
Transistors,MosFET ,Diode,Integrated circuits

M2004-01 View Datasheet(PDF) - Integrated Circuit Systems

Part Name
Description
Manufacturer
M2004-01
ICST
Integrated Circuit Systems ICST
M2004-01 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
Micro Networks
An Integrated Circuit Systems Company
M2004-01
Preliminary Specifications
FUNCTIONAL BLOCK DIAGRAM
The internal PLL will adjust the VCSO output
frequency to be M times the selected input
reference clock frequency. Note that the product of
M x input frequency must be such that it falls within
the “lock” range of the VCSO. The N output divider
can be programmed to divide the VCSO output
frequency by 1, 2, 4, or 8 and provide a 50% output
duty cycle.
REF_CLK1
REF_CLK0
REF_SEL
S_DATA
S_CLK
S_LOAD
nP_LOAD
RLOOP CLOOP
M2004-01
OP_IN
Phase
MUX Detector RIN
1
0
RIN
RLOOP CLOOP
nOP_IN OP_OUT
Loop Filter
Amplifier
M Divider
M = 3-1023
Serial / Parallel
Configuration Register
RPOST
RPOST
CPOST
CPOST
nOP_OUT nVC VC
External
Loop Filter
Components
SAW Delay Line
Phase
Shifter
VCSO
N Divider
N = 1,2,4,8
FOUT
nFOUT
6
2
M5:0
N1:0
MR
The M2004-01 supports both parallel and serial
operating modes for programming the M divider
and N output divider. Figure 1 shows the timing
diagram for each mode. In the parallel mode the
nP_LOAD input is initially LOW. The data on inputs
M0 through M5 and N0 and N1 is passed directly to
the M divider. On the LOW-to-HIGH transition of
the nP_LOAD input, the data is latched and the M
divider remains loaded until the next LOW transition
on nP_LOAD or until a serial event occurs. As a
result, the M and N bits can be hardwired to set the
M divider and N output divider to a specific default
state that will automatically occur during power-up.
The relationship between the VCSO frequency, the
input REF_CLK , and the M divider is defined as
follows:
F VCSO = F REF_CLK x M
When the N output divider is included, the
complete relationship for the output frequency is
defined as:
FOUT= F VCSO = F REF_CLK x M
N
N
The M value and the required logic states of M0
through M5 are shown in Table 5B, Programmable
VCSO Frequency Function Table. (i.e. For an output
frequency of 622.0800MHz and an input frequency
of 19.44MHz the M value would be 32 and the N
value would be 1.
Similarly, for an output frequency of 311.04MHz
and an input frequency of 19.44 MHz the M value
would be 32 and the N value would be 2.) Serial
operation occurs when nP_LOAD is HIGH and
S_LOAD is LOW. The shift register is loaded by
sampling the S_DATA bits with the rising edge of
S_CLOCK. The contents of the shift register are
loaded into the M divider and N output divider
when S_LOAD transitions from LOW-to-HIGH. The
M divider and N output divide values are latched on
the HIGH-to-LOW transition of S_LOAD. If S_LOAD
is held HIGH, data at the S_DATA input is passed
directly to the M divider and N output divider on
each rising edge of S_CLOCK.
FIGURE 1
S_DATA Low Low Null N1 N0 Null Null Null M5 M4 M3 M2 M1 M0
S_CLK
S_LOAD
Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com
2
 

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]