GS840Z18AT-180I View Datasheet(PDF) - Giga Semiconductor

Part Name

Description

Manufacturer

GS840Z18AT-180I

4Mb Pipelined and Flow Through Synchronous NBT SRAMs

Giga Semiconductor 

GS840Z18/36AT-180/166/150/100

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by its internal pull-down resistor. When ZZ is pulled high,

the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to

low, the SRAM operates normally after 2 cycles of wake up time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of

Sleep Mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become

disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.

When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated

until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands

may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

tKH

tKC

tKL

CK

tZZS

tZZH

tZZR

ZZ

Designing for Compatibility

The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal

found on Pin 14. Not all vendors offer this option, however, most mark Pin 14 as VDD or VDDQ on pipelined parts and VSS on flow

through parts. GSI NBT SRAMs are fully compatible with these sockets.

Pin 66, a No Connect (NC) on GSI’s GS840Z18/36A NBT SRAM, the Parity Error open drain output on GSI’s GS881Z18/36 NBT

SRAM, is often marked as a power pin on other vendor’s NBT-compatible SRAMs. Specifically, it is marked VDD or VDDQ on

pipelined parts and VSS on flow through parts. Users of GSI NBT devices who are not actually using the ByteSafe™ parity feature

may want to design the board site for the RAM with Pin 66 tied high through a 1k ohm resistor in Pipeline mode applications or

tied low in Flow Through mode applications in order to keep the option to use non-configurable devices open. By using the pull-up

resistor, rather than tying the pin to one of the power rails, users interested in upgrading to GSI’s ByteSafe NBT SRAMs

(GS881Z18/36), featuring Parity Error detection and JTAG Boundary Scan, will be ready for connection to the active low, open

drain Parity Error output driver at Pin 66 on GSI’s TQFP ByteSafe RAMs.

Rev: 1.03 11/2004

12/24

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2001, GSI Technology

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