AD7904BRUZ-REEL7 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD7904BRUZ-REEL7 Datasheet PDF : 32 Pages
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Data Sheet
AD7904/AD7914/AD7924
TIMING SPECIFICATIONS
AVDD = 2.7 V to 5.25 V, VDRIVE ≤ AVDD, REFIN = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1
fSCLK2
tCONVERT
tQUIET
AVDD = 3 V
10
20
16 × tSCLK
50
t2
10
t3 3
35
t4 3
40
t5
0.4 × tSCLK
t6
0.4 × tSCLK
t7
10
t8 4
15/45
t9
10
t10
5
t11
20
t12
1
Limit at TMIN, TMAX
AVDD = 5 V
Unit
10
kHz min
20
MHz max
16 × tSCLK
50
ns min
10
30
40
0.4 × tSCLK
0.4 × tSCLK
10
15/35
10
5
20
1
ns min
ns max
ns max
ns min
ns min
ns min
ns min/ns max
ns min
ns min
ns min
μs max
Description
Minimum quiet time required between the CS rising edge and the start
of the next conversion
CS to SCLK setup time
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to DOUT valid hold time
SCLK falling edge to DOUT high impedance
DIN setup time prior to SCLK falling edge
DIN hold time after SCLK falling edge
16th SCLK falling edge to CS high
Power-up time from full shutdown/auto shutdown modes
1 Sample tested @ 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V (see Figure 2).
The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × VDRIVE.
4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
200µA
IOL
TO
OUTPUT
PIN
CL
50pF
1.6V
200µA
IOH
Figure 2. Load Circuit for Digital Output Timing Specifications
Rev. C | Page 9 of 32
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