LPC1763FBD100 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
LPC1763FBD100
NXP Semiconductors.
LPC1763FBD100 Datasheet PDF : 79 Pages
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NXP Semiconductors
5. Block diagram
LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
debug
port
JTAG
interface
RMII pins
USB pins
XTAL1
XTAL2
RESET
TEST/DEBUG
INTERFACE
ARM
CORTEX-M3
I-code D-code
bus
bus
LPC1769/68/67/
66/65/64/63
DMA
CONTROLLER
ETHERNET
CONTROLLER
WITH DMA(1)
system
bus
master
master
USB PHY
USB HOST/
DEVICE/OTG
CONTROLLER
WITH DMA(1)
master
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
clocks and
controls
slave
ROM
slave
MULTILAYER AHB MATRIX
SRAM 32/64 kB
CLKOUT
P0 to
P4
SCK1
SSEL1
MISO1
MOSI1
RXD0/TXD0
8 × UART1
RD1/2
TD1/2
SCL0/1
SDA0/1
SCK/SSEL
MOSI/MISO
2 × MAT0/1
2 × CAP0/1
PWM1[7:0]
PCAP1[1:0]
AD0[7:0]
P0, P2
RTCX1
RTCX2
VBAT
HIGH-SPEED
GPIO
slave
APB slave group 0
SSP1
slave
AHB TO
APB
BRIDGE 0
UART0/1
CAN1/2(1)
I2C0/1
SPI0
TIMER 0/1
WDT
PWM1
12-bit ADC
PIN CONNECT
GPIO INTERRUPT CONTROL
32 kHz
OSCILLATOR
RTC
BACKUP REGISTERS
RTC POWER DOMAIN
(1) Not available on all parts. See Table 2.
Fig 1. Block diagram
slave
slave
FLASH
ACCELERATOR
AHB TO
APB
BRIDGE 1
FLASH
512/256/128 kB
APB slave group 1
SSP0
UART2/3
I2S(1)
I2C2
RI TIMER
TIMER2/3
EXTERNAL INTERRUPTS
SYSTEM CONTROL
MOTOR CONTROL PWM
DAC(1)
QUADRATURE ENCODER
= connected to DMA
SCK0
SSEL0
MISO0
MOSI0
RXD2/3
TXD2/3
3 × I2SRX
3 × I2STX
TX_MCLK
RX_MCLK
SCL2
SDA2
4 × MAT2
2 × MAT3
2 × CAP2
2 × CAP3
EINT[3:0]
MCOA[2:0]
MCOB[2:0]
MCI[2:0]
MCABORT
AOUT
PHA, PHB
INDEX
002aad944
LPC1769_68_67_66_65_64_63
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 5 April 2011
© NXP B.V. 2011. All rights reserved.
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