UL634H256
Disabeling Automatic STORES: STORE Cycle Inhibit and Automatic Power Up RECALL
VCAP
3.0 V
VSWITCH
Power Up
RECALL
(24)
tRESTORE
t
STORE inhibit
+
100 µF 0.1 µF
± 20 % Bypass
VCAP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VSS 16
VCCX
32
31
30 HSB
29
28
27
26
25
24
23
22
21
20
19
18
17
Power
Supply
10 kΩ
(optional,
see description HSB
nonvolatile store)
Figure 1: Automatic STORE Operation
Schematic Diagram
0.1 µF
Bypass
VCAP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VSS 16
VCCX
32
31
30 HSB
29
28
27
26
25
24
23
22
21
20
19
18
17
Power
Supply
10 kΩ
(optional,
see description HSB
nonvolatile store)
Figure 2: Disabeling Automatic STORES
Schematic Diagram
Low Average Active Power
The UL634H256 has been designed to draw signifi-
cantly less power when E is LOW (chip enabled) but
the access cycle time is longer than 55 ns.
When E is HIGH the chip consumes only standby cur-
rent.
The overall average current drawn by the part depends
on the following items:
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
5. the operating temperature
6. the power supply voltage level
The information describes the type of component and shall not be considered as assured characteristics. Terms of
delivery and rights to change design reserved.
January 09, 2002
13