U637256 View Datasheet(PDF) - Unspecified
Part Name
Description
Manufacturer
U637256 Datasheet PDF : 14 Pages
| |||
U637256
PowerStore and automatic Power Up RECALL
VCC
5.0 V
VSWITCH
PowerStore
Power Up
RECALL
W
DQi
(24)
tRESTORE
t
(25)
tPDSTORE
(24)
tRESTORE
tDELAY
POWER UP BROWN OUT
BROWN OUT
RECALL
NO STORE
PowerStore
(NO SRAM WRITES)
No.
Software Controlled STORE/RECALL
Cyclek, o
Symbol
Alt.
IEC
Min.
Max.
Unit
27 STORE/RECALL Initiation Time
tAVAV
tcR
70
28 Chip Enable to Output Inactivep
tELQZ
tdis(E)SR
29 STORE Cycle Timeq
tELQXS
td(E)S
30 RECALL Cycle Timer
tELQXR
td(E)R
31 Address Setup to Chip Enables
tAVELN
tsu(A)SR
0
32 Chip Enable Pulse Widths, t
tELEHN
tw(E)SR
60
33 Chip Disable to Address Changes
tEHAXN
th(A)SR
0
ns
600
ns
10
ms
20
μs
ns
ns
ns
o: The software sequence is clocked with E controlled READs.
p: Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
q: Note that STORE cycles (but not RECALL) are inhibited by VCC < VSWITCH (STORE inhibit).
r: An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below
VSWITCH once it has been exceeded for the RECALL to function properly.
s: Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
t: If the Chip Enable Pulse Width is less than ta(E) (see Read Cycle) but greater than or equal tw(E)SR, than the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
STK Control #ML0054
8
Rev 1.0
March 31, 2006
|
|
Share Link: 