U634H256D1M25 View Datasheet(PDF) - Zentrum Mikroelektronik Dresden AG
Part Name
Description
Manufacturer
U634H256D1M25 Datasheet PDF : 14 Pages
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U634H256
PowerStore 32K x 8 nvSRAM
Features
Description
! High-performance CMOS non-
volatile static RAM 32768 x 8 bits
! 25, 35 and 45 ns Access Times
! 10, 15 and 20 ns Output Enable
Access Times
! ICC = 15 mA typ. at 200 ns Cycle
Time
! Automatic STORE to EEPROM
on Power Down using external
capacitor
! Hardware or Software initiated
STORE
(STORE Cycle Time < 10 ms)
! Automatic STORE Timing
! 105 STORE cycles to EEPROM
! 10 years data retention in
EEPROM
! Automatic RECALL on Power Up
! Software RECALL Initiation
(RECALL Cycle Time < 20 µs)
! Unlimited RECALL cycles from
EEPROM
! Single 5 V ± 10 % Operation
! Operating temperature ranges:
0 to 70 °C
-40 to 85 °C
-40/-55 to 125 °C (only 35 ns)
! QS 9000 Quality Standard
! ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
! Packages: SOP32 (300 mil),
PDIP32 (600 mil, only C/K-Type)
The U634H256 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The U634H256 is a fast static RAM
(25, 35, 45 ns), with a nonvolatile
electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
using charge stored in an external
100 µF capacitor.
Transfers from the EEPROM to the
SRAM (the RECALL operation)
take place automatically on power
up.
The U634H256 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
STORE cycles also may be initia-
ted under user control via a soft-
ware sequence or via a single pin
(HSB).
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Pin Configuration
VCAP
A14
A12
A7
A6
A5
A4
A3
n.c.
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
32
2
31
3
30
4
29
5
28
6
27
7 PDIP 26
8
25
9 SOP 24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
VCCX
HSB
W
A13
A8
A9
A11
G
n.c.
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Pin Description
Signal Name
A0 - A14
DQ0 - DQ7
E
G
W
VCCX
VSS
VCAP
HSB
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
Capacitor
Hardware Controlled Store/Busy
Top View
April 21, 2004
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