ST10F269Z2QX View Datasheet(PDF) - STMicroelectronics
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ST10F269Z2QX Datasheet PDF : 161 Pages
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ST10F269Z2Qx
Instructions and Commands
All operations besides normal read operations are
initiated and controlled by command sequences
written to the Flash Command Interface (CI). The
Command Interface (CI) interprets words written
to the Flash memory and enables one of the
following operations:
– Read memory array
– Program Word
– Block Erase
– Chip Erase
– Erase Suspend
– Erase Resume
– Block Protection
– Block Temporary Unprotection
– Code Protection
Commands are composed of several write cycles
at specific addresses of the Flash memory. The
different write cycles of such command
sequences offer a fail-safe feature to protect
against an inadvertent write.
A command only starts when the Command
Interface has decoded the last write cycle of an
operation. Until that last write is performed, Flash
memory remains in Read Mode
Notes: 1. As it is not possible to perform write
operations in the Flash while fetching code
from Flash, the Flash commands must be
written by instructions executed from
internal RAM or external memory.
2. Command write cycles do not need to
be consecutively received, pauses are
allowed, save for Block Erase command.
During this operation all Erase Confirm
commands must be sent to complete any
block erase operation before time-out
period expires (typically 96µs). Command
sequencing must be followed exactly. Any
invalid combination of commands will reset
the Command Interface to Read Mode.
Status Register
This register is used to flag the status of the
memory and the result of an operation. This
register can be accessed by read cycles during
the Erase-Program Controller (EPC) operation.
Erase Operation
This Flash memory features a block erase
architecture with a chip erase capability too.
Erase is accomplished by executing the six cycle
erase command sequence. Additional command
write cycles can then be performed to erase more
than one block in parallel. When a time-out period
elapses (96µs) after the last cycle, the
Erase-Program Controller (EPC) automatically
starts and times the erase pulse and executes the
erase operation. There is no need to program the
block to be erased with ‘0000h’ before an erase
operation. Termination of operation is indicated in
the Flash status register. After erase operation,
the Flash memory locations are read as 'FFFFh’
value.
Erase Suspend
A block erase operation is typically executed
within 1.5 second for a 64K Byte block. Erasure of
a memory block may be suspended, in order to
read data from another block or to program data in
another block, and then resumed.
In-System Programming
In-system programming is fully supported. No
special programming voltage is required. Because
of the automatic execution of erase and
programming algorithms, write operations are
reduced to transferring commands and data to the
Flash and reading the status. Any code that
programs or erases Flash memory locations (that
writes data to the Flash) must be executed from
memory outside the on-chip Flash memory itself
(on-chip RAM or external memory).
A boot mechanism is provided to support
in-system programming. It works using serial link
via USART interface and a PC compatible or
other programming host.
Read/Write Protection
The Flash module supports read and write
protection in a very comfortable and advanced
protection functionality. If Read Protection is
installed, the whole Flash memory is protected
against any "external" read access; read
accesses are only possible with instructions
fetched directly from program Flash memory. For
update of the Flash memory a temporary disable
of Flash Read Protection is supported.
The device also features a block write protection.
Software locking of selectable memory blocks is
provided to protect code and data. This feature
will disable both program and erase operations in
the selected block(s) of the memory. Block
Protection is accomplished by block specific
lock-bit which are programmed by executing a
four cycle command sequence. The locked state
of blocks is indicated by specific flags in the
according block status registers. A block may only
be temporarily unlocked for update (write)
operations.
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