PM8610 View Datasheet(PDF) - PMC-Sierra, Inc

Part Name

Description

Manufacturer

PM8610

SBI Bus Serializer (SBS)

PMC-Sierra, Inc 

SBS Telecom Standard Product Data Sheet

Preliminary

Pin Name

D[15]

D[14]

D[13]

D[12]

D[11]

D[10]

D[9]

D[8]

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

A[8]/TRS

A[7]

A[6]

A[5]

A[4]

A[3]

A[2]

A[1]

A[0]

ALE

Type

I/O

Input

Input

Pin No.

AE20

AD19

AF16

AD15

AE15

AF15

AD14

AC11

AD10

AF6

AC8

AD7

AF4

AC6

AD5

AE4

AF3

AC5

AD4

AD1

AC2

AB3

AA4

AA3

Y3

AA23

INTB

Open

N3

Drain

Output

General Function (9 Signals)

SYSCLK

Input

D6

SREFCLK19 Output

B4

Function

Microprocessor Data Bus. The bi-directional data bus, D[15:0] is

used during SBS Microprocessor Interface Port register reads and

write accesses. D[15] is the most significant bit of the data words

and D[0] is the least significant bit.

Microprocessor Address Bus. The microprocessor address bus

(A[8:0]) selects specific Microprocessor Interface Port registers

during SBS register accesses.

A[8] is also the Test Register Select (TRS) address pin and selects

between normal and test mode register accesses. TRS is set high

during test mode register accesses, and is set low during normal

mode register accesses.

Address Latch Enable. The address latch enable signal (ALE) is

active high and latches the address bus (A[11:0]) when it is set low.

The internal address latches are transparent when ALE is set high.

ALE allows the SBS to interface to a multiplexed address/data bus.

ALE has an integral pull up resistor.

Interrupt Request Bar. The active low interrupt enable signal

(INTB) output goes low when an SBS interrupt source is active and

that source is unmasked. INTB returns high when the interrupt is

acknowledged via an appropriate register access. INTB is an open

drain output.

SBI System Clock. The 77 MHz SBI reference clock signal,

SYSCLK, is the master clock for the SBS device. SYSCLK is a

77.76 MHz clock, with a nominal 50% duty cycle. RC1FP,

RDATA[7:0], RDP, RPL, RV5, RTPL, RTAIS and RJUST_REQ are

sampled on the rising edge of SYSCLK. TC1FP, TDATA[7:0],

TDP, TPL, TV5, TTPL, TAIS and TJUST_REQ are updated on the

rising edge of SYSCLK.

19.44 MHz SBI Reference Clock. The19.44 MHz SBI reference

clock signal, SREFCLK19, is a reference for 19.44 MHz SBI bus

and TelecomBus interfaces. SREFCLK19 is a 19.44 MHz clock,

with a nominal 50% duty cycle and is generated from the 77.76

MHz SYSCLK.

When the incoming and outgoing buses are running at 19.44 MHz,

this signal should be tied to SREFCLK.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

46

Document ID: PMC-2000168, Issue 3

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